Voltage controlled oscillator

Abstract

A voltage controlled oscillator generating an oscillation signal according to a first control signal without a silent region. The voltage controlled oscillator includes a control signal adjuster and a plurality of delay cells. The control signal adjuster receives the first control signal and generates a second and a third control signal according to the first control signal. The voltage level of the third control signal is higher than that of the second control signal and the voltage level of the second control signal is higher than that of the first control signal. The plurality of delay cells are ring-connected and controlled by the first, the second, and the third control signals to generate the oscillation signal. Each delay cell includes three sets of current generation transistors. The three sets of current generation transistors are separately controlled by the three different control signals.

What is claimed is: 
     
       1. A voltage controlled oscillator generating an oscillation signal according to a first control signal, comprising:
 a control signal adjuster, receiving the first control signal and generating a second control signal and a third control signal according to the first control signal, wherein the second control signal is generated to be higher than a voltage level of the first control signal and the third control signal is generated to be higher than a voltage level of the second control signal; and 
 a plurality of delay cells, ring-connected and controlled by the first, the second, and the third control signals to generate the oscillation signal, wherein each delay cell comprises:
 a first set of current generation transistors, wherein each transistor provides a control terminal to receive the first control signal; 
 a second set of current generation transistors, wherein each transistor provides a control terminal to receive the second control signal; and 
 a third set of current generation transistors, wherein each transistor provides a control terminal to receive the third control signal. 
 
 
     
     
       2. The voltage controlled oscillator as claimed in  claim 1 , wherein the second control signal is generated to be higher than the voltage level of the first control signal by approximately a first threshold voltage and the third control signal is generated to be higher than the voltage level of the second control signal by approximately a second threshold voltage. 
     
     
       3. The voltage controlled oscillator as claimed in  claim 1 , wherein the control signal adjuster comprises:
 a current mirror, generating a first mirror current and a second mirror current according to a current source; 
 a tenth P-channel transistor, having a source coupled to the first mirror current, a gate coupled to the first control signal, and a drain coupled to ground; and 
 an eleventh P-channel transistor, having a source coupled to the second mirror current, a gate coupled to the source of the tenth P-channel transistor, and a drain coupled to ground, 
 wherein the second control signal is generated at the source of the tenth P-channel transistor and the third control signal is generated at the source of the eleventh P-channel transistor. 
 
     
     
       4. The voltage controlled oscillator as claimed in  claim 3 , wherein the current mirror comprises:
 a seventh P-channel transistor, having a source coupled to a voltage source, a gate and a drain both coupled to the current source; 
 an eighth P-channel transistor, having a source coupled to the voltage source, a gate coupled to the gate of the seventh P-channel transistor, and a drain generating the first mirror current; and 
 a ninth P-channel transistor, having a source coupled to the voltage source, a gate coupled to the gate of the seventh P-channel transistor, and a drain generating the second mirror current. 
 
     
     
       5. The voltage controlled oscillator as claimed in  claim 1 , wherein each of the delay cells further comprises a differential input/output circuit coupled to the first, the second and the third sets of current generation transistors, wherein the differential input/output circuit comprises:
 a third P-channel transistor, having a gate working as a first differential input terminal, a source coupled to a voltage source, and a drain; 
 a fourth P-channel transistor, having a gate working as a second differential input terminal, a source coupled to the voltage source, and a drain; 
 a fifth P-channel transistor, having a gate coupled to the drain of the fourth P-channel transistor to work as a first differential output terminal, a source coupled to the voltage source, and a drain coupled to the drain of the third P-channel transistor; and 
 a sixth P-channel transistor, having a gate coupled to the drain of the third P-channel transistor to work as a second differential output terminal, a source coupled to the voltage source, and a drain coupled to the drain of the fourth P-channel transistor. 
 
     
     
       6. The voltage controlled oscillator as claimed in  claim 5 , wherein:
 the first set of current generation transistors of each delay cell comprises:
 a first N-channel transistor, having a gate receiving the first control signal, a source coupled to ground, and a drain coupled to the drains of the third and the fifth P-channel transistors; and 
 a second N-channel transistor, having a gate receiving the first control signal, a source coupled to the ground, and a drain coupled to the drains of the fourth and the sixth P-channel transistors; 
 
 the second set of current generation transistors of each delay cell comprises:
 a third N-channel transistor, having a gate receiving the second control signal, a source coupled to the ground, and a drain coupled to the drains of the third and the fifth P-channel transistors; and 
 a fourth N-channel transistor, having a gate receiving the second control signal, a source coupled to the ground, and a drain coupled to the drains of the fourth and the sixth P-channel transistors; and 
 
 the third set of current generation transistors of each delay cell comprises:
 a fifth N-channel transistor, having a gate receiving the third control signal, a source coupled to ground, and a drain coupled to the drains of the third and the fifth P-channel transistors; and 
 a sixth N-channel transistor, having a gate receiving the third control signal, a source coupled to the ground, and a drain coupled to the drains of the fourth and the sixth P-channel transistors. 
 
 
     
     
       7. The voltage controlled oscillator as claimed in  claim 5 , wherein, for each delay cell, the first and the second differential output terminals thereof are coupled to the first and the second differential input terminals of a next delay cell. 
     
     
       8. A voltage controlled oscillator generating an oscillation signal according to a first control signal, comprising:
 a control signal adjuster, receiving the first control signal and generating a second control signal and a third control signal according to the first control signal, wherein the second control signal is generated to be higher than a voltage level of the first control signal and the third control signal is generated to be higher than a voltage level of the second control signal; and 
 a plurality of ring-connected delay cells, receiving the first, the second and the third control signals to generate the oscillation signal at a first differential output terminal of one of the plurality of the ring-connected delay cells, wherein, for each ring-connected delay cell, the first differential output terminal and a second differential output terminal thereof are coupled to a first differential input terminal and a second differential input terminal of a next ring-connected delay cell. 
 
     
     
       9. The voltage controlled oscillator as claimed in  claim 8 , wherein the second control signal is generated to be higher than the voltage level of the first control signal by approximately a first threshold voltage and the third control signal is generated to be higher than the voltage level of the second control signal by approximately a second threshold voltage. 
     
     
       10. The voltage controlled oscillator as claimed in  claim 8 , wherein the control signal adjuster comprises:
 a current mirror, generating a first mirror current and a second mirror current 
 a tenth P-channel transistor, having a source coupled to the first mirror current, a gate coupled to the first control signal, and a drain coupled to ground; and 
 an eleventh P-channel transistor, having a source coupled to the second mirror current, a gate coupled to the source of the tenth P-channel transistor, and a drain coupled to ground, 
 wherein the second control signal is generated at the source of the tenth P-channel transistor and the third control signal is generated at the source of the eleventh P-channel transistor. 
 
     
     
       11. The voltage controlled oscillator as claimed in  claim 10 , wherein the current mirror comprises:
 a seventh P-channel transistor, having a source coupled to a voltage source, a gate and a drain both coupled to the current source; 
 an eighth P-channel transistor, having a source coupled to the voltage source, a gate coupled to the gate of the seventh P-channel transistor, and a drain generating the first mirror current; and 
 a ninth P-channel transistor, having a source coupled to the voltage source, a gate coupled to the gate of the seventh P-channel transistor, and a drain generating the second mirror current. 
 
     
     
       12. The voltage controlled oscillator as claimed in  claim 8 , wherein each of the delay cells further comprises a differential input/output circuit coupled to the first, the second and the third sets of current generation transistors, wherein the differential input/output circuit comprises:
 a third P-channel transistor, having a gate working as the first differential input terminal, a source coupled to a voltage source, and a drain; 
 a fourth P-channel transistor, having a gate working as the second differential input terminal, a source coupled to the voltage source, and a drain; 
 a fifth P-channel transistor, having a gate coupled to the drain of the fourth P-channel transistor to work as the first differential output terminal, a source coupled to the voltage source, and a drain coupled to the drain of the third P-channel transistor; and 
 a sixth P-channel transistor, having a gate coupled to the drain of the third P-channel transistor to work as the second differential output terminal, a source coupled to the voltage source, and a drain coupled to the drain of the fourth P-channel transistor. 
 
     
     
       13. The voltage controlled oscillator as claimed in  claim 12 , wherein:
 the first set of current generation transistors of each delay cell comprises:
 a first N-channel transistor, having a gate receiving the first control signal, a source coupled to ground, and a drain coupled to the drains of the third and the fifth P-channel transistors; and 
 a second N-channel transistor, having a gate receiving the first control signal, a source coupled to the ground, and a drain coupled to the drains of the fourth and the sixth P-channel transistors; 
 
 the second set of current generation transistors of each delay cell comprises:
 a third N-channel transistor, having a gate receiving the second control signal, a source coupled to the ground, and a drain coupled to the drains of the third and the fifth P-channel transistors; and 
 a fourth N-channel transistor, having a gate receiving the second control signal, a source coupled to the ground, and a drain coupled to the drains of the fourth and the sixth P-channel transistors; and 
 
 the third set of current generation transistors of each delay cell comprises:
 a fifth N-channel transistor, having a gate receiving the third control signal, a source coupled to ground, and a drain coupled to the drains of the third and the fifth P-channel transistors; and 
 a sixth N-channel transistor, having a gate receiving the third control signal, a source coupled to the ground, and a drain coupled to the drains of the fourth an d the sixth P-channel transistors.