Memory devices and operating methods for a memory device

Abstract

Devices and methods facilitate memory device operation in all bit line architecture memory devices. In at least one embodiment, memory cells comprising alternating rows are concurrently programmed by row and concurrently sensed by row at a first density whereas memory cells comprising different alternating rows are concurrently programmed by row and concurrently sensed by row at a second density. In at least one additional embodiment, memory cells comprising alternating tiers of memory cells are programmed and sensed by tier at a first density and memory cells comprising different alternating tiers of memory cells are programmed and sensed by tier at a second density.

What is claimed is: 
     
       1. A method of operating a memory device having an array of memory cells logically arranged in tiers and in columns where each column is coupled to a respective one of a plurality of data lines and where each tier comprises a plurality of rows of memory cells, the method comprising:
 concurrently programming a selected memory cell of each row of memory cells comprising a first tier of memory cells at a first density; and 
 concurrently programming a selected memory cell of each row of memory cells comprising a second tier of memory cells at a second density different than the first density. 
 
     
     
       2. The method of  claim 1 , further comprising concurrently programming a selected memory cell of each row of memory cells comprising a third tier of memory cells at a third density different than the first density and the second density. 
     
     
       3. The method of  claim 1 , wherein concurrently programming a selected memory cell of each row of memory cells comprising the first tier of memory cells at a first density further comprises programming each memory cell of the first tier of memory cells as single level memory cells, and where concurrently programming a selected memory cell of each row of memory cells comprising the second tier of memory cells at a second density further comprises programming each memory cell of the second tier of memory cells as multilevel memory cells. 
     
     
       4. The method of  claim 1 , wherein concurrently programming a selected memory cell of each row of memory cells comprising the first tier of memory cells at a first density further comprises programming each memory cell of the first tier of memory cells as multilevel cells having a first level, and where concurrently programming a selected memory cell of each row of memory cells comprising the second tier of memory cells at a second density further comprises programming each memory cell of the second tier of memory cells as multilevel memory cells having a second level. 
     
     
       5. The method of  claim 1 , wherein each row of the first tier of memory cells comprises two or more adjacent memory cells commonly coupled to a first access line, and where each row of the second tier of memory cells comprises two or more adjacent memory cells commonly coupled to a second access line. 
     
     
       6. The method of  claim 5 , wherein memory cells comprising the first tier of memory cells are commonly coupled to the first access line, and where memory cells comprising the second tier of memory cells are commonly coupled to the second access line. 
     
     
       7. The method of  claim 6 , wherein each memory cell of the first tier of memory cells shares a source/drain region with a corresponding memory cell of the second tier of memory cells. 
     
     
       8. The method of  claim 1 , further comprising concurrently programming a selected memory cell of each row of memory cells comprising a third tier of memory cells at the first density, wherein the first tier of memory cells is adjacent to the second tier of memory cells and where the second tier of memory cells is adjacent to the third tier of memory cells. 
     
     
       9. The method of  claim 8 , further comprising concurrently programming a selected memory cell of each row of memory cells comprising a fourth tier of memory cells at the second density, wherein the third tier of memory cells is adjacent to the fourth tier of memory cells. 
     
     
       10. A method of operating a memory device having an array of memory cells logically arranged in tiers and in columns where each column is coupled to a respective one of a plurality of data lines and where each tier comprises a plurality of rows of memory cells, the method comprising:
 concurrently programming a selected memory cell of each row of memory cells comprising a first tier of memory cells to a respective one of a first number of data states; and 
 concurrently programming a selected memory cell of each row of memory cells comprising a second tier of memory cells to a respective one of a second number of data states after programming a selected memory cell of each row of memory cells comprising the first tier of memory cells; 
 wherein the first number of data states is different than the second number of data states; 
 wherein at least one column of the array of memory cells comprises a memory cell of the first tier of memory cells and a memory cell of the second tier of memory cells. 
 
     
     
       11. An apparatus, comprising:
 an array of memory cells logically arranged in tiers and in columns, where each column is coupled to a respective data line and where each tier comprises a plurality of rows of memory cells commonly coupled to a respective access line; and 
 a controller, wherein the controller is configured to cause a selected memory cell of each row of memory cells comprising a first tier of memory cells to be concurrently programmed to a respective one of a first number of data states, and to cause a selected memory cell of each row of memory cells comprising a second tier of memory cells to be concurrently programmed to a respective one of a second number of data states; 
 wherein the first number of data states is different than the second number of data states. 
 
     
     
       12. The apparatus of  claim 11 , wherein the controller is further configured to cause a selected memory cell of each row of memory cells comprising a third tier of memory cells to be concurrently programmed to a respective one of the first number of data states, where the second tier of memory cells is between the first tier of memory cells and the third tier of memory cells. 
     
     
       13. The apparatus of  claim 11 , wherein each data line comprises a bit line and where the memory array comprises a three-dimensional (3D) all bit line (ABL) architecture memory array. 
     
     
       14. The apparatus of  claim 11 , wherein the controller is further configured to cause each memory cell of the first tier of memory cells to be programmed to a respective one of the first number of data states, and to cause each memory cell of the second tier of memory cells to be programmed to a respective one of the second number of data states. 
     
     
       15. The apparatus of  claim 11 , wherein the controller is further configured to cause each memory cell comprising a first number of alternating tiers of memory cells to be programmed to a respective one of the first number of data states, and to cause each memory cell comprising a second number of alternating tiers of memory cells to be programmed to a respective one of the second number of data states. 
     
     
       16. A memory device, comprising:
 an array of memory cells logically arranged in tiers and in columns, where each column is coupled to a respective data line and where each tier comprises a plurality of rows of memory cells commonly coupled to a respective access line; and 
 a controller, wherein the controller is configured to cause a selected memory cell of each row of memory cells comprising a first tier of memory cells to be concurrently programmed as single level memory cells, and to cause a selected memory cell of each row of memory cells comprising a second tier of memory cells to be concurrently programmed as multi-level memory cells; 
 wherein the first tier of memory cells comprises two or more adjacent memory cells commonly coupled to a first access line; 
 wherein the second tier of memory cells comprises two or more adjacent memory cells commonly coupled to a second access line; and 
 wherein each memory cell of the first tier of memory cells shares a drain/source region with a corresponding memory cell of the second tier of memory cells. 
 
     
     
       17. The memory device of  claim 16 , wherein the controller is further configured to cause a first plurality of alternating tiers of memory cells to be programmed as single level memory cells and to cause a second plurality of alternating tiers of memory cells to be programmed as multi-level memory cells.