Method for manufacturing semiconductor device with first and second gates over buried bit line

Abstract

A semiconductor device and a method for manufacturing the same are provided. The method includes forming a cell structure where a storage node contact is coupled to first and second channel layers formed on sidewalls and upper portions of a plurality of gates, thereby simplifying the manufacturing process of the device. The semiconductor device includes a bit line buried in a semiconductor substrate; the gates disposed over the semiconductor substrate buried with the bit line; a first plug disposed in a lower portion between the gates and coupled to the bit line; and a second plug coupled to the second channel layer.

What is claimed is: 
     
       1. A method for manufacturing a semiconductor device, the method comprising:
 forming a buried bit line in a substrate; 
 forming an interlayer insulating pattern over the buried bit line; 
 forming a first channel layer at both sides of the interlayer insulating pattern; and 
 forming a conductive material in a gate-expected region to form a gate, wherein the gate-expected region is disposed at a side of the first channel layer. 
 
     
     
       2. The method of  claim 1 , the method further comprising:
 before the forming the interlayer insulating pattern, 
 forming a first plug over the buried bit line to be coupled to the buried bit line, wherein the first plug is disposed between the interlayer insulating pattern and the buried bit line. 
 
     
     
       3. The method of  claim 2 , wherein the interlayer insulating pattern is formed to be disposed over a middle portion of the first plug. 
     
     
       4. The method of  claim 3 , wherein the forming the first channel layer includes:
 growing a first silicon layer at both sides of the interlayer insulating pattern; and 
 removing a portion of the first silicon layer in the gate-expected region so that the first silicon layer remains over an edge of the first plug. 
 
     
     
       5. The method of  claim 1 , wherein the forming the first channel layer includes:
 growing a first silicon layer at both sides of the interlayer insulating pattern; and 
 removing a portion of the first silicon layer in the gate-expected region so that the first silicon layer remains at both sides of the interlayer insulating pattern. 
 
     
     
       6. The method of  claim 1 , the method further comprising:
 after forming the gate, 
 forming a second plug over a portion of the first channel layer to be coupled to the first channel layer. 
 
     
     
       7. The method of  claim 6 , wherein the forming the second plug includes:
 forming a second channel layer over the first channel layer and the gate to be coupled to the first channel layer; and 
 forming a conductive material over the second channel layer. 
 
     
     
       8. The method of  claim 7 , wherein the forming the second channel layer includes:
 growing a second silicon layer over the first channel layer and the gate. 
 
     
     
       9. The method of  claim 8 , wherein the second silicon layer is grown by using the first channel layer as a seed.