Fast exit from self-refresh state of a memory device

Abstract

A system provides for a signal to indicate when a memory device exits from self-refresh. Thus, substantially at the same time (before or after) the memory device exits self-refresh, an indicator signal can be triggered to indicate normal operation or standard refresh operation and normal memory access of the memory device. A memory controller can access the indicator signal to determine whether the memory device is in self-refresh. Thus, the memory controller can more carefully manage the timing of sending a command to the memory device while reducing the delay time typically associated with detecting a self-refresh condition.

What is claimed is: 
     
       1. A method comprising:
 fast exiting from a self-refresh mode of memory resources to store data, wherein a fast exit time for the fast exiting is a time after an exit from self-refresh until a valid command can be issued to the memory resources, wherein the fast exit time is shorter than a refreshed cycle time (tRFC) for the memory resources plus an additional guard band time for the memory resources, wherein the fast exit time is based on periodically polling a self-refresh state indicator at a period of time. 
 
     
     
       2. The method of  claim 1 , further comprising setting a state of a configuration bit to enable the fast exiting. 
     
     
       3. The method of  claim 1 , wherein fast exiting includes changing from the self-refresh mode to a standard refresh mode of a memory device, where the self-refresh mode disables a clock within the memory device to temporarily suspend access operations of the memory device; and further comprising:
 triggering a self-refresh state indicator of the memory device responsive to changing from the self-refresh state to the standard refresh state. 
 
     
     
       4. The method of  claim 3 , wherein changing is triggered by memory resource control logic coupled to the memory resources. 
     
     
       5. The method of  claim 3 , wherein changing from the self-refresh state to the standard refresh state comprises:
 changing states in response to a self-refresh timer. 
 
     
     
       6. The method of  claim 3 , wherein triggering the self-refresh state indicator comprises:
 setting a pin of the memory device. 
 
     
     
       7. The method of  claim 3 , wherein triggering the self-refresh state indicator comprises:
 sending a self-refresh status message to a memory controller. 
 
     
     
       8. The method of  claim 1 , wherein the period of time is based on one of (1) a maximum timing specification for the memory resources, (2) a defined mode of DLL bypass that allows asynchronous operation of the memory resources while the DLL is locking in the background, (3) a hardware specific characteristic of the memory resources based on architecture and manufacturing of the memory resources, or (4) device density of the memory resources. 
     
     
       9. An apparatus comprising:
 memory resources to store data; and 
 memory resource control logic coupled to the memory resources, the memory resource control logic to enable a fast exit from a self-refresh mode, a fast exit time is a time after an exit from self-refresh until a valid command can be issued to the memory resources, wherein the fast exit time is shorter than a refreshed cycle time (tRFC) for the memory resources plus an additional guard band time for the memory resources, wherein the fast exit time is based on periodically polling a self-refresh state indicator at a period of time. 
 
     
     
       10. The apparatus of  claim 9 , wherein a state of a configuration bit enables fast exit mode. 
     
     
       11. The apparatus of  claim 9 , further comprising:
 an input control line to receive a clock signal; and 
 the control logic to:
 change from the self-refresh state to a standard refresh state, where the self-refresh state disables the clock within the memory resources to temporarily suspend access operations of the memory resources; and 
 switch a self-refresh state indicator responsive to changing from the self-refresh state to the standard refresh state. 
 
 
     
     
       12. The apparatus of  claim 11 , wherein the memory resources comprise memory resources of a memory bank within a memory device. 
     
     
       13. The apparatus of  claim 11 , wherein the control logic to switch the self-refresh state indicator comprises:
 control logic to set a pin of the apparatus to a logic state corresponding to the standard refresh state. 
 
     
     
       14. The apparatus of  claim 11 , wherein the control logic to switch the self-refresh indicator comprises:
 control logic to send a self-refresh status message to a memory controller. 
 
     
     
       15. The apparatus of  claim 9 , wherein the period of time is based on one of (1) a maximum timing specification for the memory resources, (2) a defined mode of DLL bypass that allows asynchronous operation of the memory resources while the DLL is locking in the background, (3) a hardware specific characteristic of the memory resources based on architecture and manufacturing of the memory resources, or (4) a device density of the memory resources. 
     
     
       16. A system comprising:
 a memory device having
 memory resources to store data; 
 memory resource control logic coupled to the memory resources, the memory resource control logic to enable a fast exit from a self-refresh mode, a fast exit time is a time after an exit from self-refresh until a valid command can be issued to the memory resources, wherein the fast exit time is shorter than a refreshed cycle time (tRFC) for the memory resources plus an additional guard band time for the memory resources, wherein the fast exit time is based on periodically polling a self-refresh state indicator at a period of time; and 
 
 a memory controller to manage access to data stored on the memory device, the memory controller to:
 determine whether to access the memory device by determining whether the self-refresh state indicator indicates the memory device is in a self-refresh state; 
 if the memory device is in the self-refresh state, select a self-refresh wait time; 
 otherwise, select a guard band wait time; where the self-refresh wait time indicates an amount of time a memory controller should wait before determining again whether the self-refresh state indicator indicates the memory device is in a self-refresh state, and the guard band wait time indicates a minimum time between commands sent to the memory device from a memory controller; and 
 send a command at the end of the guard band wait time. 
 
 
     
     
       17. The system of  claim 16 , wherein a state of a configuration bit enables fast exit mode. 
     
     
       18. The system of  claim 16 , further comprising:
 an input control line to receive a clock signal; and 
 the control logic to:
 change from the self-refresh state to a standard refresh state, where the self-refresh state disables the clock within the memory resources to temporarily suspend access operations of the memory resources; and 
 switch a self-refresh state indicator responsive to changing from the self-refresh state to the standard refresh state. 
 
 
     
     
       19. The system of  claim 18 , wherein the control logic to switch the self-refresh state indicator comprises:
 control logic to set a pin of the apparatus to a logic state corresponding to the standard refresh state, wherein the pin comprises a bidirectional clock enable (CKE) channel, wherein the memory device drives the channel to indicate exit from self-refresh, and wherein otherwise the memory controller drives the channel; and 
 wherein the memory controller to select the self-refresh wait time comprises: 
 the memory controller to select a wait time between performing polling attempts of the self-refresh state indicator to determine whether to access the memory device. 
 
     
     
       20. The system of  claim 16 , wherein the period of time is based on one of (1) a maximum timing specification for the memory resources, (2) a defined mode of DLL bypass that allows asynchronous operation of the memory resources while the DLL is locking in the background, (3) a hardware specific characteristic of the memory resources based on architecture and manufacturing of the memory resources, or (4) a device density of the memory resources.