Charge distribution control for secure systems

Abstract

Advantageous analog and/or digital logic cells and methods of powering circuit blocks using the same are provided. A digital logic cell can include a charge storage device, a logic block, and connections to a power supply. The charge storage device may be a capacitor. The capacitor or other charge storage device can be disconnected from the logic block and a power supply to discharge the capacitor, and then connected to the power supply, via the power supply connections, to charge the capacitor. The capacitor can be disconnected from a ground connection of the power supply while the capacitor is discharged. After being charged via the power supply, the capacitor can also be disconnected from the power supply (including ground) and connected to the logic block to power the logic block.

We claim: 
     
       1. A secure digital logic cell of an integrated circuit (IC) chip, comprising:
 a logic cell; and 
 a charge storage device on the IC chip and controllably connected and disconnected from a high supply rail of the logic cell, a low supply rail of the logic cell, a high voltage rail connection of a power supply and a low voltage rail or ground connection of the power supply to isolate the logic cell from the power supply. 
 
     
     
       2. The secure digital logic cell of  claim 1 , wherein the charge storage device is further controllably discharged by shorting a positive terminal and a negative terminal of the charge storage device together. 
     
     
       3. The secure digital logic cell of  claim 2 , wherein the charge storage device is fully discharged periodically between each logic operation of the logic cell or a predetermined number of logic operations of the logic cell. 
     
     
       4. The secure digital logic cell according to  claim 1 , wherein the logic cell comprises a plurality of transistors each having a body terminal, and wherein the body terminal of each transistor within the logic cell is coupled to at least one of the high supply rail of the logic cell and the low supply rail of the logic cell. 
     
     
       5. The secure digital logic cell according to  claim 1 , wherein the logic cell comprises at least one transistor formed in an isolated well. 
     
     
       6. The secure digital logic cell according to  claim 1 , wherein the charge storage device is a discrete capacitor, a MOS capacitor, a MOS transistor, or a charge coupled device. 
     
     
       7. A charge distribution control system, comprising:
 a plurality of charge storage devices, each charge storage device providing power to a corresponding circuit element during operation of the corresponding circuit element; and 
 a charge distribution controller, wherein the charge distribution controller connects each charge storage device to a power supply during a charging operation and connects each charge storage device to the corresponding circuit element during operation of the corresponding circuit element, wherein during an operation of one of the charge storage devices' corresponding circuit element, that charge storage device is not connected to a power and ground connection of the power supply. 
 
     
     
       8. The charge distribution control system of  claim 7 , wherein at least one of the corresponding circuit elements comprises an analog circuit block. 
     
     
       9. The charge distribution control system of  claim 7 , wherein at least one of the corresponding circuit elements comprises a digital logic block. 
     
     
       10. The charge distribution control system of  claim 7 , wherein the charge distribution controller further disconnects each charge storage device from both the power supply and the corresponding circuit element during a discharging operation for that charge storage device. 
     
     
       11. The charge distribution control system of  claim 7 , wherein the charge distribution controller comprises a clock generator that controls the connections of each charge storage device. 
     
     
       12. The charge distribution control system of  claim 11 , wherein, for each storage device, the clock generator generates a first clock for a first switch for discharging that charge storage device, a second clock for a second switch for connecting and disconnecting that charge storage device to the power connection of the power supply and a third switch for connecting and disconnecting that charge storage device to the ground connection of the power supply; and a third clock for a fourth switch for connecting and disconnecting that charge storage device to a power connection of the logic cell and a fifth switch for connecting and disconnecting that charge storage device to a ground connection of the logic cell. 
     
     
       13. The charge distribution control system of  claim 7 , wherein the charge distribution controller comprises a delay circuit that controls the connections of each charge storage device. 
     
     
       14. A method of protecting against at least one side channel attack from the group consisting of differential power analysis, simple power analysis, leakage current analysis, differential electromagnetic field analysis, timing analysis, heat, acoustic analysis, fault injection and differential fault analysis, the method comprising:
 operating the charge distribution control system of  claim 7 .