Method for manufacturing a carbon nanotube field emission device with overhanging gate

Abstract

A carbon nanotube field emission device with overhanging gate fabricated by a double silicon-on-insulator process. Other embodiments are described and claimed.

What is claimed is: 
     
       1. A semiconductor process applied to a wafer, the wafer comprising a silicon substrate; a first insulator layer on the silicon substrate; a first silicon layer on the first insulator layer; a second insulator layer on the first silicon layer; and a second silicon layer on the second insulator layer; the semiconductor process comprising:
 etching through the second silicon layer, through the second insulator layer, and through the first silicon layer to the first insulator layer to define a hole; 
 lateral etching in the first silicon layer to laterally enlarge the hole at the first silicon layer; 
 etching through the first insulator layer to the substrate, so that the hole has a bottom that includes the substrate; 
 depositing a removable material on the wafer; and 
 forming an array of carbon nanotubes at the bottom of the hole on the substrate. 
 
     
     
       2. The semiconductor process as set forth in  claim 1 , where the depositing the removable material on the wafer comprises depositing the removable material on the substrate at the bottom of the hole. 
     
     
       3. The semiconductor process as set forth in  claim 2 , where forming the array of carbon nanotubes at the bottom of the hole on the substrate further comprises:
 patterning the removable material to provide a pattern for a catalyst; depositing the catalyst on the substrate at the bottom of the hole; and growing the array of carbon nanotubes on the catalyst. 
 
     
     
       4. The semiconductor process as set forth in  claim 3  further comprising removing the removable material from the wafer after depositing the catalyst on the substrate at the bottom of the hole and before growing the array of carbon nanotubes on the catalyst. 
     
     
       5. The semiconductor process as set forth in  claim 1 , where depositing the removable material comprises depositing the removable material on the wafer so that the removable material bridges the opening of the hole. 
     
     
       6. The semiconductor process as set forth in  claim 5 , where forming the array of carbon nanotubes at the bottom of the hole on the substrate further comprises: patterning the removable material to provide a pattern for a catalyst; depositing the catalyst on the substrate at the bottom of the hole; and growing the array of carbon nanotubes on the catalyst. 
     
     
       7. The semiconductor process as set forth in  claim 6 , where patterning the removable material to provide a pattern for a catalyst comprises forming a plurality of openings through which the catalyst for carbon nanotube formation is adapted to be deposited onto the bottom of the hole on the substrate. 
     
     
       8. The semiconductor process as set forth in  claim 6 , where the catalyst is comprised within a catalyst dot array. 
     
     
       9. The semiconductor process as set forth in  claim 1 , where the removable material is a photoresist material. 
     
     
       10. The semiconductor process as set forth in  claim 1 , further comprising depositing a second material on the wafer after removing the removable material from the wafer. 
     
     
       11. The semiconductor process as set forth in  claim 10 , where the second material comprises sol-gel material or micro glass-blowing material. 
     
     
       12. The semiconductor process as set forth in  claim 11 , where the micro glass-blowing material is a sol-gel or epoxy material. 
     
     
       13. The semiconductor process as set forth in  claim 1 , where the first and second insulator layers comprise silicon dioxide. 
     
     
       14. The semiconductor process as set forth in  claim 1 , where the second silicon layer forms a gate with respect to at least one carbon nanotubes in the array of carbon nanotubes at the bottom of the hole on the substrate. 
     
     
       15. The semiconductor process as set forth in  claim 1 , where the hole has a top and a sidewall, the second silicon layer forming at least a portion of the sidewall wherein the second silicon layer at the top of the hole overhangs the sidewall.