High voltage semiconductor device and the associated method of manufacturing

Abstract

The present disclosure discloses a high voltage semiconductor device and the associated methods of manufacturing. In one embodiment, the high voltage semiconductor device comprises: an epitaxial layer, a first low voltage well formed in the epitaxial layer; a second low voltage well formed in the epitaxial layer; a high voltage well formed in the epitaxial layer, wherein the second low voltage well is surrounded by the high voltage well; a first highly doping region formed in the first low voltage well; a second highly doping region and a third highly doping region formed in the second low voltage well, wherein the third highly doping region is adjacent to the second highly doping region; a field oxide formed in the epitaxial layer as a shallow-trench isolation structure; and a gate region formed on the epitaxial layer.

We claim: 
     
       1. A high voltage PMOS, comprising:
 a P-type epitaxial layer; 
 an N-type buried layer under the epitaxial layer; 
 a P-type first low voltage well acting as a drain body region, wherein the first low voltage well is formed in the epitaxial layer; 
 an N-type second low voltage well acting as a source body region, wherein the second low voltage well is formed in the epitaxial layer; 
 an N-type high voltage well acting as a supporting body region, wherein the high voltage well is formed in the epitaxial layer, and wherein the second low voltage well is surrounded by the high voltage well, and further wherein the first low voltage well and the high voltage well are not adjacent and separated by the epitaxial layer; 
 a P-type first highly doping region, wherein the first highly doping region is formed in the first low voltage well; 
 a P-type second highly doping region, wherein the second highly doping region is formed in the second low voltage well; 
 an N-type third highly doping region, wherein the third highly doping region is formed in the second low voltage well, and wherein the third highly doping region is adjacent to the second highly doping region; 
 a field oxide formed in the epitaxial layer as a shallow-trench isolation structure; and 
 a gate region formed on the epitaxial layer. 
 
     
     
       2. The high voltage PMOS of  claim 1 , wherein the second low voltage well has a higher doping concentration than that of the high voltage well. 
     
     
       3. The high voltage PMOS of  claim 1 , further comprising:
 a drain electrode contacted with the first highly doping region; and 
 a source electrode contacted with both the second highly doping region and the third highly doping region. 
 
     
     
       4. A high voltage PMOS, comprising:
 a P-type epitaxial layer; 
 an N-type buried layer under the epitaxial layer; 
 a P-type first low voltage well acting as a drain body region, wherein the first low voltage well is formed in the epitaxial layer; 
 an N-type second low voltage well acting as a source body region, wherein the second low voltage well is formed in the epitaxial layer; 
 an N-type high voltage well acting as a supporting body region, and wherein the second low voltage well is surrounded by the high voltage well, and further wherein the first low voltage well and the high voltage well are not adjacent and separated by the epitaxial layer; 
 a P-type first highly doping region, wherein the first highly doping region is formed in the first low voltage well; 
 a P-type second highly doping region, wherein the second highly doping region is formed in the second low voltage well; 
 an N-type third highly doping region, wherein the third highly doping region is formed in the second low voltage well, and wherein the third highly doping region is adjacent to the second highly doping region; 
 a field oxide formed on the epitaxial layer; and 
 a gate region formed on the epitaxial layer and on the field oxide. 
 
     
     
       5. The high voltage PMOS of  claim 4 , further comprising:
 a drain electrode contacted with the first highly doping region; and 
 a source electrode contacted with both the second highly doping region and the third highly doping region. 
 
     
     
       6. The high voltage PMOS of  claim 4 , wherein the second low voltage well has a higher doping concentration than that of the high voltage well.