Digital transmitter

Abstract

An equalizer provided in a digital transmitter compensates for attenuation in a signal channel to a digital receiver. The equalizer generates signal levels as a logical function of bit history to emphasize transition signal levels relative to repeated signal levels. The preferred equalizer includes an FIR transition filter using a look-up table. Parallel circuits including FIR filters and digital-to-analog converters provide a high speed equalizer with lower speed circuitry. The equalizer is particularly suited to in-cabinet and local area network transmissions where feedback circuitry facilitates adaptive training of the equalizer.

What is claimed is: 
     
       1. A semiconductor device for use in transmitting a signal over a conductive path to a receiver, the semiconductor device comprising:
 a semiconductor chip; and 
 equalization circuitry, including programmable circuitry, and a drive circuit, on the semiconductor chip; 
 the equalization circuitry to receive input bits and generate a sequence of signal levels, at least one signal level per input bit but no more than two signal levels per input bit, each signal level a logical function of bits of the input bits, the signal levels in the sequence to be generated so as to emphasize transitions between adjacent bits of the inputs bits while attenuating repeated values of adjacent bits of the input bits; 
 the drive circuit to drive the sequence of signal levels onto the conductive path; 
 the programmable circuitry to cause a particular set of tap weight settings, for at least three taps to be used by the equalization circuitry to generate the signal levels in the sequence, in response to measured line characteristics associated with the conductive path. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the semiconductor device supports a training mode, wherein the semiconductor device further comprises circuitry to generate a signal pattern comprising ones and zeroes for the drive circuit to transmit to the receiver during the training mode, the ones and zeroes alternated in a manner to test multiple bit rates, and wherein the programmable circuitry is to receive programming to define the particular set of tap weight settings to be used by the equalization circuitry responsive to the transmission of the signal pattern during the training mode. 
     
     
       3. The semiconductor device of  claim 1 , wherein the at least three taps include a main tap, a precursor tap and a postcursor tap. 
     
     
       4. The semiconductor device of  claim 1 , wherein the at least three taps are collectively used to generate each signal level in the sequence. 
     
     
       5. The semiconductor device of  claim 1 , wherein the conductive path is a differential path, and wherein:
 the drive circuit is to transmit a serial output signal to the receiver in a manner that conveys the signal levels in the sequence using full current drive in opposite directions on both sides of each transition between adjacent bits of the input bits, as a differential signal. 
 
     
     
       6. The semiconductor device of  claim 5 , wherein:
 the equalization circuitry and the drive circuit are implemented as a standard cell, and define a single serial port of the semiconductor device; and 
 the semiconductor device comprises plural ones of the single serial port, each having an instance of the equalization circuitry and the drive circuit, implemented so as to transmit a sequence of signal levels over a respective differential path. 
 
     
     
       7. The semiconductor device of  claim 1 , wherein the semiconductor device further comprises circuitry to receive n parallel bits, and to encode the parallel bits to generate m of the input bits in response to the n parallel bits, where m is greater than n, so as to ensure a minimum transition density in the input bits. 
     
     
       8. The semiconductor device of  claim 1 , wherein the programmable circuitry includes a lookup table, and wherein the equalization circuitry is to use the logical function of the bit of the input bits to access the lookup table and the lookup table is to responsively yield a drive strength. 
     
     
       9. The semiconductor device of  claim 1 , wherein the signal levels of the sequence are to vary in frequency over a range that includes Rmax, Rmax/2 and Rmax/3, where Rmax represents an alternating sequence of ones and zeros in the input bits. 
     
     
       10. The semiconductor device of  claim 1 , wherein the drive circuit includes pulse generators. 
     
     
       11. A semiconductor device for use in transmitting a signal over a conductive path to a receiver, the semiconductor device comprising:
 a semiconductor chip; 
 equalization circuitry, including programmable circuitry, a drive circuit, and circuitry to generate a signal pattern on the semiconductor chip; 
 the equalization circuitry to receive input bits and generate a sequence of signal levels, at least one signal level per input bit but no more than two signal levels per input bit, each signal level a logical function of bits of the input bits, the signal levels in the sequence to be generated so as to emphasize transitions between adjacent bits of the inputs bits while attenuating repeated values of adjacent bits of the input bits; 
 the drive circuit to drive the sequence of signal levels onto the conductive path; 
 the programmable circuitry to cause a particular set of tap weight settings, for at least three taps to be used by the equalization circuitry to generate the signal levels in the sequence, in response to measured line characteristics associated with the conductive path, the at least three taps including a precursor tap and a postcursor tap; 
 the signal pattern comprising ones and zeroes for the drive circuit to transmit to the receiver during the training mode, the ones and zeroes alternated by the circuitry to generate the pattern in a manner to test multiple bit rates; 
 the programmable circuitry to receive programming, to define the particular set of tap weight settings to be used by the equalization circuitry, responsive to the transmission of the signal pattern during a training mode of the semiconductor device. 
 
     
     
       12. The semiconductor device of  claim 11 , wherein the conductive path is a differential path, and wherein:
 the drive circuit is to transmit a serial, differential output signal to the receiver over the differential path in a manner that conveys the sequence of signal levels using full current drive in opposite directions on both sides of each transition between adjacent bits of the input bits. 
 
     
     
       13. The semiconductor device of  claim 11 , wherein:
 the equalization circuitry, the drive circuit and the circuitry to generate the signal pattern are implemented as a standard cell, and define a single serial port of the semiconductor device; and 
 the semiconductor device comprises plural ones of the single serial port, each having an instance of the equalization circuitry, the drive circuit and the circuitry to generate the signal pattern, implemented so as to transmit a sequence of signal levels over a respective differential path. 
 
     
     
       14. The semiconductor device of  claim 11 , wherein the semiconductor device further comprises circuitry to receive n parallel bits, and to encode the parallel bits to generate m of the input bits in response to the n parallel bits, where m is greater than n, so as to ensure a minimum transition density in the input bits. 
     
     
       15. A semiconductor device for use in transmitting a signal over a conductive, differential path to a receiver, the semiconductor device comprising:
 a semiconductor chip; and 
 encoding circuitry, equalization circuitry, including programmable circuitry, and a drive circuit on the semiconductor chip; 
 the encoding circuitry to receive n parallel bits and to encode the parallel bits to generate m input bits in response to the n parallel bits, where m is greater than n, so as to generate the m input bits in a manner that ensures a minimum transition density; 
 the equalization circuitry to receive m input bits and generate a sequence of signal levels, at least one signal level per input bit but no more than two signal levels per input bit, each signal level a logical function of bits of the input bits, the signal levels in the sequence to be generated so as to emphasize transitions between adjacent bits of the m inputs bits while attenuating repeated values of adjacent bits of the m input bits; 
 the drive circuit to drive the sequence of signal levels onto the conductive, differential path as a serial output signal; 
 the programmable circuitry to cause a particular set of tap weight settings, for at least three taps to be used by the equalization circuitry to generate the signal levels in the sequence, in response to measured line characteristics associated with the conductive path. 
 
     
     
       16. The semiconductor device of  claim 15 , wherein the semiconductor device supports a training mode, wherein the semiconductor device further comprises circuitry to generate a signal pattern comprising ones and zeroes for the drive circuit to transmit to the receiver during the training mode, the ones and zeroes alternated in a manner to test multiple bit rates, and wherein the programmable circuitry is to receive programming to define the particular set of tap weight settings to be used by the equalization circuitry responsive to the transmission of the signal pattern during the training mode. 
     
     
       17. The semiconductor device of  claim 15 , wherein the at least three taps include a main tap, a precursor tap and a postcursor tap. 
     
     
       18. The semiconductor device of  claim 15 , wherein the at least three taps are collectively used to generate each signal level in the sequence. 
     
     
       19. The semiconductor device of  claim 15 , wherein:
 the encoding circuitry, the equalization circuitry, and the drive circuit are implemented as a standard cell, and define a single serial port of the semiconductor device; and 
 the semiconductor device comprises plural ones of the single serial port, each having an instance of the encoding circuitry, the equalization circuitry, and the drive circuit, implemented so as to transmit a sequence of signal levels over a respective differential path. 
 
     
     
       20. The semiconductor device of  claim 15 , wherein the signal levels of the sequence are to vary in frequency over a range that includes Rmax, Rmax/2 and Rmax/3, where Rmax represents an alternating sequence of ones and zeros in the m input bits. 
     
     
       21. The semiconductor device of  claim 15 , wherein there is exactly one signal level in the sequence of signal levels for each of the m input bits.