Low-power inverter-based differential amplifier

Abstract

A new inverter-based fully-differential amplifier is provided including one or more common-mode feedback transistors coupled to each inverter, which transistors operate in the liner region. Accordingly, due to the fully-differential nature of the new inverter-based fully-differential amplifier, the amplifier provides an improved Power Supply Rejection Ratio (PSRR), provides a reduced sensitivity to supply voltage and process or part variations, and does not require an auto-zeroing technique to be utilized, which ultimately saves power, all while utilizing the low-voltage and low-power advantages of an inverter-based design.

What is claimed is: 
     
       1. An apparatus comprising:
 a class-AB rail-to-rail low voltage amplifier comprising:
 a first CMOS inverter configured to receive a first signal representative of a first half of a differential input signal; 
 a second CMOS inverter configured to receive a second signal representative of a second half of the differential input signal; 
 at least a first CMOS transistor coupled to the first CMOS inverter and configured to operate as a common-mode feedback control, wherein the at least a first CMOS transistor operates in a linear mode; 
 at least a second CMOS transistor coupled to the second CMOS inverter and configured to operate as a common-mode feedback control, wherein the at least a second CMOS transistor operates in a linear mode; 
 
 wherein the class-AB rail-to-rail low-voltage amplifier is configured to output a fully differential output signal. 
 
     
     
       2. The apparatus of  claim 1  wherein a positive supply of the first CMOS inverter and a positive supply of the second CMOS inverter are coupled and wherein a negative supply of the first CMOS inverter and a negative supply of the second CMOS inverter are coupled. 
     
     
       3. The apparatus of  claim 2  wherein the class-AB rail-to-rail low-voltage amplifier is configured to output the fully differential output signal having a PSRR of greater than approximately 40 dB without utilizing an auto-zeroing technique. 
     
     
       4. The apparatus of  claim 1  wherein the at least a first CMOS transistor coupled to the first CMOS inverter further comprises:
 a first p-channel transistor configured to operate in a linear region, wherein:
 a drain of the first p-channel transistor is operatively coupled to the positive supply of the first CMOS inverter; 
 a gate of the first p-channel transistor is operatively coupled to a first output signal of the fully differential output signal; and 
 a source of the first p-channel transistor is operatively coupled to a positive power supply; and 
 
 a first n-channel transistor configured to operate in a linear region, wherein:
 a drain of the first n-channel transistor is operatively coupled to the negative supply of the first CMOS inverter; 
 a gate of the first n-channel transistor is operatively coupled to the first output signal; and 
 a source of the first n-channel transistor is operatively coupled to a negative power supply; and 
 
 
       wherein the at least a second CMOS transistor coupled to the second CMOS inverter further comprises:
 a second p-channel transistor configured to operate in a linear region, wherein:
 a drain of the second p-channel transistor is operatively coupled to the positive supply of the second CMOS inverter; 
 a gate of the second p-channel transistor is operatively coupled to a second output signal of the fully differential output signal; and 
 a source of the second p-channel transistor is operatively coupled to the positive power supply; and 
 
 a second n-channel transistor configured to operate in a linear region, wherein:
 a drain of the second n-channel transistor is operatively coupled to the negative supply of the second inverter; 
 a gate of the second n-channel transistor is operatively coupled to the second output signal; and 
 a source of the second n-channel transistor is operatively coupled to the negative power supply; 
 
 
       and wherein the positive supply of the first CMOS inverter and the positive supply of the second CMOS inverter are coupled and wherein the negative supply of the first CMOS inverter and the negative supply of the second CMOS inverter are coupled. 
     
     
       5. The apparatus of  claim 1  wherein the class-AB rail-to-rail low voltage amplifier further comprises a fully differential operational transconductance amplifier. 
     
     
       6. A method comprising:
 at a class-AB rail-to-rail low-voltage CMOS inverter-based amplifier:
 receiving an input signal for processing to create an output signal; 
 using linear mode common-mode feedback control to reduce a common-mode signal on the output signal of the class-AB rail-to-rail low-voltage CMOS inverter-based amplifier; 
 outputting the output signal comprising a fully differential output signal having a Power Supply Rejection Ratio (PSRR) of greater than approximately 40 dB; 
 wherein the class-AB rail-to-rail low-voltage amplifier is configured to output the fully differential output signal having a PSRR of greater than approximately 40 dB when operating in a non-auto-zeroing configuration. 
 
 
     
     
       7. The method of  claim 6  wherein receiving an input signal for processing to create an output signal further comprises:
 a first CMOS inverter outputting a first half of the fully differential output signal by outputting a first output current relating to an approximate inverse of a first half of the input signal; and 
 a second CMOS inverter outputting a second half of the fully differential output signal by outputting a second output current relating to an approximate inverse of a second half of the input signal. 
 
     
     
       8. The method of  claim 6  wherein receiving an input signal for processing to create an output signal further comprises receiving a differential input signal comprising a first half of the differential input signal and a second half of the differential input signal. 
     
     
       9. The method of  claim 6  wherein receiving the input signal for processing to create an output signal further comprises:
 at a first CMOS inverter:
 receiving a first half of the input signal; 
 outputting a first half of the fully differential output signal; 
 
 at a second CMOS inverter:
 receiving a second half of the input signal; 
 outputting a second half of the fully differential output signal; 
 
 wherein a positive supply of the first CMOS inverter and a positive supply of the second CMOS inverter are operatively coupled to form a positive node and a negative supply of the first CMOS inverter and a negative supply of the second CMOS inverter are operatively coupled to form a negative node; and 
 
       wherein using linear mode common-mode feedback control to reduce the common-mode signal on the output signal of the class-AB rail-to-rail low-voltage CMOS inverter-based amplifier further comprises:
 adjusting a resistance between the positive node and a positive voltage supply with a first p-channel transistor and a second p-channel transistor, wherein the first and second p-channel transistors are each configured to operate in a linear region and wherein the gate of the first p-channel transistor is operatively coupled to the first half of the fully differential output signal and wherein the gate of the second p-channel transistor is operatively coupled to the second half of the fully differential output signal; and 
 adjusting a resistance between the negative node and a negative voltage supply with a first n-channel transistor and a second n-channel transistor, wherein the first and second n-channel transistors are each configured to operate in a linear region, and wherein a gate of the first n-channel transistor is coupled to the first half of the fully differential output signal and a gate of the second n-channel transistor is coupled to the second half of the fully differential output signal, and wherein the first and second n-channel transistors are configured to operate in a linear region. 
 
     
     
       10. The method of  claim 9  further comprising:
 at a third CMOS inverter:
 receiving the first half of the fully differential output signal; 
 outputting a first half of a second stage output signal; 
 
 at a fourth CMOS inverter:
 receiving the second half of the fully differential output signal; 
 outputting a second half of the second stage output signal; 
 
 wherein a positive supply of the third CMOS inverter and a positive supply of the fourth CMOS inverter are operatively coupled to form a second positive node and a negative supply of the third CMOS inverter and a negative supply of the fourth CMOS inverter are operatively coupled to form a second negative node; 
 at the second positive node:
 adjusting a resistance between the second positive node and the positive voltage supply with a third p-channel transistor and a fourth p-channel transistor, wherein the third and fourth p-channel transistors are in parallel and each configured to operate in a linear region and wherein a gate of the third p-channel transistor is operatively coupled to at least one of the first half of the second stage output signal and a common mode signal, and wherein a gate of the fourth p-channel transistor is operatively coupled to at least one of the second half of the second stage output signal and the common mode signal; and 
 
 at the second negative node:
 adjusting a resistance between the second negative node and the negative voltage supply with a third n-channel transistor and a fourth n-channel transistor, wherein the third and fourth p-channel transistors are in parallel and each configured to operate in a linear region and wherein a gate of the third n-channel transistor is operatively coupled to the first half of the second stage output signal and a gate of the fourth n-channel transistor is operatively coupled to the second half of the second stage output signal. 
 
 
     
     
       11. The method of  claim 10  further comprising:
 at a common mode amplifier:
 receiving a desired common mode signal; 
 receiving an average of the first half of the second stage output signal and the second half of the second stage output signal; and 
 amplifying the common mode of the first half of the second stage output signal and the second half of the second stage output signal by amplifying the difference between the received desired common mode signal and the received average of the first half of the second stage output signal and the second half of the second stage output signal to generate the common mode signal. 
 
 
     
     
       12. An apparatus comprising:
 a first inverter comprising:
 an input configured to receive a first input signal; 
 an output configured to output a first output signal; 
 a positive supply; and 
 a negative supply; 
 
 a second inverter comprising:
 an input configured to receive a second input signal: 
 an output configured to output a second output signal; 
 a positive supply; and 
 a negative supply; 
 wherein the positive supply of the second inverter is operatively coupled to the positive supply of the first inverter and the negative supply of the second inverter is operatively coupled to the negative supply of the first inverter; 
 
 a first p-channel transistor configured to operate in a linear region, wherein:
 a drain of the first p-channel transistor is operatively coupled to the positive supply of the first inverter; 
 a gate of the first p-channel transistor is operatively coupled to the first output signal; and 
 a source of the first p-channel transistor is operatively coupled to a positive power supply; 
 
 a second p-channel transistor configured to operate in a linear region, wherein:
 a drain of the second p-channel transistor is operatively coupled to the positive supply of the second inverter; 
 a gate of the second p-channel transistor is operatively coupled to the second output signal; and 
 a source of the second p-channel transistor is operatively coupled to the positive power supply; 
 
 a first n-channel transistor configured to operate in a linear region, wherein:
 a drain of the first n-channel transistor is operatively coupled to the negative supply of the first inverter; 
 a gate of the first n-channel transistor is operatively coupled to the first output signal; and 
 a source of the first n-channel transistor is operatively coupled to a negative power supply; 
 
 a second n-channel transistor configured to operate in a linear region, wherein:
 a drain of the second n-channel transistor is operatively coupled to the negative supply of the second inverter; 
 a gate of the second n-channel transistor is operatively coupled to the second output signal; and 
 a source of the second n-channel transistor is operatively coupled to the negative power supply; 
 
 wherein the first output signal and the second output signal together comprise a fully differential signal. 
 
     
     
       13. The apparatus of  claim 12  wherein the apparatus comprises a fully differential operational transconductance amplifier. 
     
     
       14. The apparatus of  claim 12  further comprising:
 a third inverter comprising:
 an input operatively coupled to the first output signal; 
 an output operatively configured to output a third output signal; 
 a positive supply; and 
 a negative supply; 
 
 a fourth inverter comprising:
 an input operatively coupled to the second output signal: 
 an output operatively configured to output a fourth output signal; 
 a positive supply; and 
 a negative supply; 
 wherein the positive supply of the fourth inverter is operatively coupled to the positive supply of the third inverter to form a second positive node and the negative supply of the fourth inverter is operatively coupled to the negative supply of the third inverter to form a second negative node; 
 
 a third p-channel transistor configured to operate in a linear region, wherein:
 a drain of the third p-channel transistor is operatively coupled to the positive supply of the third inverter; 
 a gate of the third p-channel transistor is operatively coupled to at least one of the third output signal and a common mode signal; and 
 a source of the third p-channel transistor is coupled to the positive power supply; 
 
 a fourth p-channel transistor configured to operate in a linear region, wherein:
 a drain of the fourth p-channel transistor is operatively coupled to the positive supply of the fourth inverter; 
 a gate of the fourth p-channel transistor is operatively coupled to at least one of the fourth output signal and the common mode signal; and 
 a source of the fourth p-channel transistor is operatively coupled to the positive power supply; 
 
 a third n-channel transistor configured to operate in a linear region, wherein:
 a drain of the third n-channel transistor is operatively coupled to the negative supply of the third inverter; 
 a gate of the third n-channel transistor is operatively coupled to the fourth output signal; and 
 a source of the third n-channel transistor is operatively coupled to the negative power supply; 
 
 a fourth n-channel transistor configured to operate in a linear region, wherein:
 a drain of the fourth n-channel transistor is operatively coupled to the negative supply of the fourth inverter; 
 a gate of the fourth n-channel transistor is operatively coupled to the third output signal; and 
 a source of the fourth n-channel transistor is operatively coupled to the negative power supply; 
 
 wherein the third output signal and the fourth output signal comprise a second fully differential signal. 
 
     
     
       15. The apparatus of  claim 14  further comprising a first compensation capacitive component operatively coupling the first output signal and the third output signal and a second compensation capacitive component operatively coupling the second output signal and the fourth output signal. 
     
     
       16. The apparatus of  claim 14  wherein:
 a substrate of a p-channel transistor of the first inverter and a substrate of a p-channel transistor of the second inverter are operatively coupled to the positive power supply; and 
 a substrate of an n-channel transistor of the first inverter and a substrate of an n-channel transistor of the second inverter are operatively coupled to the negative power supply. 
 
     
     
       17. The apparatus of  claim 14  further comprising:
 a common mode amplifier configured to receive a desired common mode signal and an average of the third output signal and the fourth output signal and output the common mode signal.