Architecture for very high-speed decision feedback sequence estimation

Abstract

A method for providing a next-cycle input sample from a decision feedback equalizer to a symbol decoder using look-ahead computations such that timing contention between the decision feedback equalizer and the symbol decoder is reduced. During a symbol period, a set of possible values is computed in the decision feedback equalizer and a set of path memory symbols is computed in the symbol decoder, the set of path memory symbols being based on a current input sample. During the same symbol period, one of the possible values is selected as the next-cycle input sample based on at least one of the next-cycle path memory symbols produced from the symbol decoder.

What is claimed is: 
     
       1. An apparatus comprising:
 a plurality of channel processors, wherein each channel processor comprises:
 a decision device operable to generate a decision value based at least in part on a compensated signal, wherein the decision value is one of a plurality of decision values and the compensated signal is one of a plurality of compensated signals; 
 a decision feedback equalizer operable to generate a correction value based at least in part on the decision value; and 
 a subtractor operable to subtract the correction value and a cancellation value from a received signal to generate a compensated signal, wherein the cancellation value is one of plurality of cancellation values; and 
 
 a multiple-channel processor operable to generate the plurality of cancellation values based at least in part on the plurality of compensated signals and the plurality of decision values. 
 
     
     
       2. The apparatus of  claim 1  wherein each decision device comprises a trellis decoder. 
     
     
       3. The apparatus of  claim 1  wherein each decision device comprises a Viterbi decoder. 
     
     
       4. The apparatus of  claim 1  wherein the decision values on which the correction values are based are tentative decisions. 
     
     
       5. The apparatus of  claim 1  wherein the cancellation values comprise crosstalk cancellation values. 
     
     
       6. The apparatus of  claim 1  wherein the decision feedback equalizer comprises a filter having a plurality of coefficients corresponding to a plurality of taps.