Printed circuit boards including strip-line circuitry and methods of manufacturing same

Abstract

A printed circuit board includes a first layer stack and a second layer stack coupled to the first layer stack. The first layer stack includes a first electrically-insulating layer, a first electrically-conductive layer, and a cut-out area defining a void that extends therethrough. The first electrically-insulating layer includes a first surface and an opposite second surface. The first electrically-conductive layer is disposed on the first surface of the first electrically-insulating layer. The second layer stack includes a second electrically-insulating layer. The second electrically-insulating layer includes a first surface and an opposite second surface. One or more electrically-conductive traces are disposed on the first surface of the second electrically-insulating layer. The printed circuit board further includes a device at least partially disposed within the cut-out area. The device is electrically-coupled to one or more of the one or more electrically-conductive traces disposed on the first surface of the second electrically-insulating layer.

What is claimed is: 
     
       1. A printed circuit board (PCB), comprising:
 a first layer stack including a first electrically-insulating layer, a first electrically-conductive layer, and a cut-out area defining a void that extends through the first layer stack, the first electrically-insulating layer including a first surface and an opposite second surface, the first electrically-conductive layer disposed on the first surface of the first electrically-insulating layer; 
 a second layer stack coupled to the first layer stack, the second layer stack including a second electrically-insulating layer, the second electrically-insulating layer including a first surface and an opposite second surface; 
 an electrically-conductive trace disposed on the first surface of the second electrically-insulating layer; 
 a device at least partially disposed within the cut-out area and electrically-coupled to the electrically-conductive trace; and 
 a sheet of electrically-conductive material including a first portion covering the cut-out area and a second portion disposed on a portion of the first surface of the first electrically-insulating layer. 
 
     
     
       2. The PCB of  claim 1 , wherein the second layer stack further includes a second electrically-conductive layer disposed on the second surface of the second electrically-insulating layer. 
     
     
       3. The PCB of  claim 1 , wherein the cut-out area is configured to receive therein at least a portion of the device. 
     
     
       4. The PCB of  claim 3 , wherein a height of the device is less than a thickness of the first electrically-insulating layer. 
     
     
       5. The PCB of  claim 3 , wherein the device includes a top surface and a bottom surface. 
     
     
       6. The PCB of  claim 5 , wherein the first electrically-conductive layer includes a first surface and an opposite second surface, and the top surface of the device is disposed below the second surface of the first electrically-conductive layer. 
     
     
       7. The PCB of  claim 6 , wherein the void defined by the cut-out area includes a first volume of void space defined between the top surface of the device and a plane containing the first surface of the first electrically-conductive layer. 
     
     
       8. The PCB of  claim 7 , further comprising dielectric material disposed in at least a portion of the first volume of void space. 
     
     
       9. The PCB of  claim 8 , further comprising a sheet of electrically-conductive material including a first portion configured to cover the cut-out area. 
     
     
       10. The PCB of  claim 9 , further comprising a third layer stack coupled to the first layer stack, the third layer stack including a third electrically-insulating layer having a first surface. 
     
     
       11. The PCB of  claim 10 , further comprising a signal layer disposed in association with the first surface of the third electrically-insulating layer. 
     
     
       12. The PCB of  claim 11 , further comprising a cut-out area defining a void that extends from the first surface of the third electrically-insulating layer to the first surface of the second electrically-insulating layer. 
     
     
       13. The PCB of  claim 3 , wherein a height of the device is greater than a height of the first layer stack. 
     
     
       14. The PCB of  claim 13 , further comprising one or more gap areas disposed in adjoining relation to the cut-out area. 
     
     
       15. The PCB of  claim 14 , wherein the one or more gap areas are configured to at least one of physically isolate the device from the first electrically-conductive layer or electrically isolate the device from the first electrically-conductive layer. 
     
     
       16. The PCB of  claim 15 , further comprising a heat sink layer disposed in association with the top surface of the device. 
     
     
       17. The PCB of  claim 1 , wherein the second surface of the first electrically-insulating layer is coupled to the first surface of the second electrically-insulating layer. 
     
     
       18. The PCB of  claim 1 , wherein the first electrically-conductive layer is a ground plane. 
     
     
       19. The PCB of  claim 1 , wherein the first electrically-conductive layer is a power plane.