Method of manufacturing a semiconductor device with two monocrystalline layers

Abstract

A method of manufacturing a semiconductor wafer, the method including: providing a first monocrystalline layer including semiconductor regions defined by a first lithography step; then overlaying the first monocrystalline layer with an isolation layer; preparing a second monocrystalline layer, after the first monocrystalline layer has been formed; transferring the second monocrystalline layer overlying the isolation layer; and then performing a second lithography step patterning portions of the first monocrystalline layer as part of forming at least one transistor in the first monocrystalline layer.

What is claimed is: 
     
       1. A method of manufacturing a semiconductor wafer, the method comprising a sequence of steps comprising:
 providing a first monocrystalline layer; 
 patterning said first monocrytalline layer; 
 overlaying said first monocrystalline layer with an isolation layer; 
 preparing a second monocrystalline layer, after said first monocrystalline layer has been formed; 
 transferring said second monocrystalline layer using ion-cut, said second monocrystalline layer overlying said isolation layer; and 
 after transferring said second monocrystalline layer, etching portions of said first monocrystalline layer as part of forming at least one transistor in said first monocrystalline layer. 
 
     
     
       2. A method of manufacturing a semiconductor wafer according to  claim 1 , wherein said at least one transistor is part of a volatile memory cell. 
     
     
       3. A method of manufacturing a semiconductor wafer according to  claim 1 , wherein said at least one transistor is part of an RRAM (Resistor Random Access Memory) or Phase Change memory cell. 
     
     
       4. A method of manufacturing a semiconductor wafer according to  claim 1 ,
 wherein said at least one transistor is part of a charge trap memory cell. 
 
     
     
       5. A method of manufacturing a semiconductor wafer according to  claim 1 , further comprising:
 constructing memory peripheral circuits underneath or overlaying said at least one transistor. 
 
     
     
       6. A method of manufacturing a semiconductor wafer according to  claim 5 ,
 wherein at least one memory select line is embedded in said second monocrystalline layer. 
 
     
     
       7. A method of manufacturing a semiconductor wafer according to  claim 1 ,
 wherein said second monocrystalline layer comprises memory cells, and 
 wherein said memory cells are of a DRAM, a resistive-RAM, or a phase-change type. 
 
     
     
       8. A method of manufacturing a semiconductor wafer, the method comprising a sequence of steps comprising:
 providing a first monocrystalline layer comprising semiconductor regions defined by a first lithography step; then 
 overlaying said first monocrystalline layer with an isolation layer; 
 preparing a second monocrystalline layer, after said first monocrystalline layer has been formed; 
 transferring said second monocrystalline layer overlying said isolation layer; and then 
 performing a second lithography step patterning portions of said first monocrystalline layer as part of forming at least one transistor in said first monocrystalline layer. 
 
     
     
       9. A method of manufacturing a semiconductor wafer according to  claim 8 , wherein said at least one transistor is part of an RRAM (Resistor Random Access Memory) or Phase Change memory cell. 
     
     
       10. A method of manufacturing a semiconductor wafer according to  claim 8 , wherein said at least one transistor is part of a volatile memory cell. 
     
     
       11. A method of manufacturing a semiconductor wafer according to  claim 8 ,
 wherein said at least one transistor is part of a charge trap memory cell. 
 
     
     
       12. A method of manufacturing a semiconductor wafer according to  claim 8 , further comprising:
 constructing memory peripheral circuits underneath or overlaying said at least one transistor. 
 
     
     
       13. A method of manufacturing a semiconductor wafer according to  claim 12 ,
 wherein at least one memory select line is embedded in said second monocrystalline layer. 
 
     
     
       14. A method of manufacturing a semiconductor wafer according to  claim 8 
 wherein said second monocrystalline layer comprises memory cells, and 
 wherein said memory cells are of a DRAM, a resistive-RAM, or a phase-change type. 
 
     
     
       15. A method of manufacturing a semiconductor wafer, the method comprising a sequence of steps comprising:
 providing a first monocrystalline layer; 
 patterning said first monocrystalline layer; 
 overlaying said first monocrystalline layer with an isolation layer; 
 preparing a second monocrystalline layer after said first monocrystalline layer has been formed, said second monocrystalline layer overlying said isolation layer; and 
 after forming said second monocrystalline layer, etching portions of said first monocrystalline layer as part of forming at least one transistor in said first monocrystalline layer,
 wherein said second monocrystalline layer comprises memory cells, and 
 wherein said memory cells are of a volatile type. 
 
 
     
     
       16. A method of manufacturing a semiconductor wafer according to  claim 15 , wherein said at least one transistor is part of a volatile memory cell. 
     
     
       17. A method of manufacturing a semiconductor wafer according to  claim 15 , wherein said at least one transistor is part of an RRAM (Resistor Random Access Memory) or Phase Change memory cell. 
     
     
       18. A method of manufacturing a semiconductor wafer according to  claim 15 , wherein at least one memory select line is embedded in said second monocrystalline layer. 
     
     
       19. A method of manufacturing a semiconductor wafer, the method comprising a sequence of steps comprising:
 providing a first monocrystalline layer; 
 patterning said first monocrystalline layer; 
 overlaying said first monocrystalline layer with an isolation layer; 
 preparing a second monocrystalline layer after said first monocrystalline layer has been formed, said second monocrystalline layer overlying said isolation layer; and 
 after forming said second monocrystalline layer, lithographically patterning portions of said first monocrystalline layer as part of forming at least one transistor in said first monocrystalline layer,
 wherein said second monocrystalline layer comprises memory cells, and 
 wherein said memory cells are of a DRAM, a resistive-RAM, or a phase-change type. 
 
 
     
     
       20. A method of manufacturing a semiconductor wafer according to  claim 19 , wherein said at least one transistor is part of a volatile memory cell. 
     
     
       21. A method of manufacturing a semiconductor wafer according to  claim 19 , wherein said preparing a second monocrystalline layer comprises an ion-cut layer transfer. 
     
     
       22. A method of manufacturing a semiconductor wafer according to  claim 19 , further comprising:
 constructing memory peripheral circuits underneath or overlaying said at least one transistor. 
 
     
     
       23. A method of manufacturing a semiconductor wafer according to  claim 19 , wherein at least one memory select line is embedded in said second monocrystalline layer.