Low power oscillator with negative resistance boosting

Abstract

Representative implementations of devices and techniques provide increased negative resistance to an oscillator circuit. A capacitance divider and/or a feedback loop may be employed to increase the negative resistance of the oscillator circuit at the same current consumption and with the same load capacitance. Further, a constant bias circuit may be employed to conserve and/or reduce the current consumption of the oscillator circuit.

What is claimed is: 
     
       1. An oscillator circuit, comprising:
 a resonator; 
 a pair of amplifier cores coupled in series, each of the amplifier cores comprising at least a first transistor device and a second transistor device; 
 a load capacitance coupled in parallel to the resonator, the load capacitance divided into a plurality of sub-capacitances, each of the sub-capacitances associated with a transistor device of the pair of amplifier cores, each sub-capacitance coupled between two nodes of the associated transistor device; and 
 at least one of a first feedback loop coupled from a drain of a first transistor device of a first amplifier core to a gate of a second transistor device of the first amplifier core and a second feedback loop coupled from a drain of a first transistor device of a second amplifier core to a gate of a second transistor device of the second amplifier core, the first feedback loop and/or the second feedback loop configured to increase a negative resistance of the oscillator circuit. 
 
     
     
       2. The circuit of  claim 1 , wherein the at least one of the first feedback loop and the second feedback loop includes at least one series capacitance. 
     
     
       3. The circuit of  claim 1 , further comprising a constant transconductance bias (gm.R) circuit arranged to reduce current consumption of the oscillator circuit, the gm.R circuit including at least one complementary metal-oxide-semiconductor (CMOS) device pair, wherein a gate of each CMOS device of the CMOS pair is coupled to a gate of a transistor device of each of the pair of amplifier cores. 
     
     
       4. The circuit of  claim 1 , wherein a desired oscillation frequency of the oscillator circuit is based on a capacitance value of the load capacitance. 
     
     
       5. The circuit of  claim 1 , wherein the plurality of sub-capacitances includes a first sub-capacitance coupled between a source and a gate of a first transistor device of a first amplifier core. 
     
     
       6. The circuit of  claim 5 , wherein the plurality of sub-capacitances includes a second sub-capacitance coupled between a source and a gate of a first transistor device of a second amplifier core, the second sub-capacitance having a substantially equivalent capacitance value to the first sub-capacitance. 
     
     
       7. The circuit of  claim 6 , wherein the plurality of sub-capacitances includes a third sub-capacitance coupled between a source and a drain of a second transistor device of the first amplifier core. 
     
     
       8. The circuit of  claim 7 , wherein the plurality of sub-capacitances includes a fourth sub-capacitance coupled between a source and a drain of a second transistor device of the second amplifier core, the fourth sub-capacitance having a substantially equivalent capacitance value to the third sub-capacitance. 
     
     
       9. An oscillator circuit, comprising:
 a resonator; 
 a load capacitance coupled in parallel to the resonator; 
 an amplifier core comprising at least a first transistor device and a second transistor device coupled in series; 
 a feedback loop coupled from a drain of the first transistor device to a gate of the second transistor device, the feedback loop arranged to increase a negative resistance of the oscillator circuit; and 
 wherein the load capacitance includes at least two sub-capacitances, a first sub-capacitance coupled between a source and a gate of the first transistor device and a second sub-capacitance coupled between a source and a drain of the second transistor device. 
 
     
     
       10. The circuit of  claim 9 , the feedback loop further comprising a series capacitance. 
     
     
       11. The circuit of  claim 9 , wherein the feedback loop is configured to couple a voltage signal at a gate of the first transistor to a source of the first transistor, the voltage signal amplified and inverted at least twice based on the coupling of the voltage signal. 
     
     
       12. The circuit of  claim 11 , wherein the negative resistance of the oscillator circuit is increased due to an increase in current through at least a portion of the load capacitance, based on the coupling of the voltage signal. 
     
     
       13. The circuit of  claim 9 , further comprising a second amplifier core coupled in series with the amplifier core, the second amplifier core comprising at least a third transistor device and a fourth transistor device coupled in series, and a second feedback loop, the second feedback loop coupled from a drain of the third transistor device to a gate of the fourth transistor device. 
     
     
       14. The circuit of  claim 13 , wherein the second feedback loop is configured to couple another voltage signal at a gate of the third transistor device to a source of the third transistor device, the other voltage signal amplified and inverted at least twice based on the coupling of the other voltage signal, and wherein the negative resistance of the oscillator circuit is increased due to an increase in current through at least a portion of the load capacitance, based on the coupling of the other voltage signal. 
     
     
       15. The circuit of  claim 13 , wherein the load capacitance is divided into a plurality of sub-capacitances, including: a first sub-capacitance coupled between a source and a gate of the first transistor device, a second sub-capacitance coupled between a gate and a source of the third transistor device, a third sub-capacitance coupled between a source and a drain of the second transistor device, and a fourth sub-capacitance coupled between a source and a drain of the fourth transistor device, and wherein the third sub-capacitance has a substantially equivalent capacitance value to the first sub-capacitance and the fourth sub-capacitance has a substantially equivalent capacitance value to the second sub-capacitance. 
     
     
       16. The circuit of  claim 15 , wherein the negative resistance of the oscillator circuit is based on a quantity of the sub-capacitances. 
     
     
       17. The circuit of  claim 13 , further comprising a constant transconductance bias (gm.R) circuit arranged to reduce current consumption by the oscillator circuit, the gm.R circuit including at least one complementary metal-oxide-semiconductor (CMOS) device pair, wherein a gate of one CMOS device of the CMOS pair is coupled to a gate of the second transistor device and a gate of another CMOS device of the CMOS pair is coupled to a gate of the fourth transistor device. 
     
     
       18. A method, comprising:
 arranging a load capacitance in parallel to a resonator of an oscillator circuit, the load capacitance comprising a plurality of sub-capacitances; 
 arranging a plurality of series-connected transistor devices to form at least one amplifier core; 
 coupling each sub-capacitance of the plurality of sub-capacitances to a transistor device of the plurality of transistor devices, each sub-capacitance coupled between two nodes of the associated transistor device; and 
 increasing a negative resistance of the oscillator circuit based on increasing a quantity of the sub-capacitances of the plurality of sub-capacitances while retaining a capacitance value of the load capacitance. 
 
     
     
       19. The method of  claim 18 , further comprising arranging at least two pairs of series-connected transistor devices to form at least two amplifier cores and coupling a sub-capacitance between two nodes of each transistor device of the at least two amplifier cores. 
     
     
       20. The method of  claim 18 , further comprising forming a plurality of inverting amplifiers using the transistor devices and one or more feedback loops, and increasing a negative resistance of the oscillator circuit based on inverting and amplifying a signal using the plurality of inverting amplifiers. 
     
     
       21. The method of  claim 18 , further comprising merging a constant bias circuit with the at least one amplifier core, and conserving a current consumed at the oscillator circuit based on the constant bias circuit. 
     
     
       22. The method of  claim 18 , wherein one or more pairs of sub-capacitances of the plurality of sub-capacitances comprise sub-capacitances having substantially equivalent capacitance values. 
     
     
       23. An oscillator circuit, comprising:
 a crystal resonator; 
 a p-type amplifier core coupled in series to an n-type amplifier core, each of the amplifier cores comprising at least two transistor devices; 
 a pair of load capacitances coupled in parallel to the crystal resonator, each of the load capacitances divided into at least two substantially equivalent sub-capacitances, each of the sub-capacitances coupled between two nodes of a transistor device of the amplifier cores; 
 a first feedback loop coupled to each of the transistor devices of the p-type amplifier core, the first feedback loop forming a first pair of inverting amplifiers using the transistor devices of the p-type amplifier core; and 
 a second feedback loop coupled to each of the transistor devices of the n-type amplifier core, the second feedback loop forming a second pair of inverting amplifiers using the transistor devices of the n-type amplifier core.