Semiconductor device with gate electrodes

Abstract

A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

What is claimed is: 
     
       1. A semiconductor device having a first memory cell and a second memory cell arranged in a first direction,
 wherein the first memory cell comprises: 
 a first gate insulating film formed over a semiconductor substrate; 
 a first gate electrode formed over the first gate insulating film; 
 a second gate insulating film formed over the semiconductor substrate and over a side wall of the first gate electrode, and including a first charge storage film; 
 a second gate electrode formed over the second gate insulating film, adjacent with the first gate electrode through the second gate insulating film; and 
 a first impurity region formed in the semiconductor substrate and positioned on a second gate electrode side, 
 wherein the second memory cell comprises: 
 a third gate insulating film formed over the semiconductor substrate; 
 a third gate electrode formed over the third gate insulating film; 
 a fourth gate insulating film formed over the semiconductor substrate and over a side wall of the third gate electrode, and including a second charge storage film; 
 a fourth gate electrode formed over the second gate insulating film, adjacent with the third gate electrode through the fourth gate insulating film; and 
 the first impurity region positioned on a fourth gate electrode side, 
 wherein the second gate electrode and the fourth gate electrode are formed in a sidewall form, 
 wherein the first gate electrode, the second gate electrode, the third gate electrode and the fourth gate electrode extend in a second direction perpendicular to the first direction, 
 wherein the second gate electrode has a first contact section extending toward the fourth gate electrode in the first direction, 
 wherein the fourth gate electrode has a second contact section extending toward the second gate electrode in the first direction, and 
 wherein the first contact section and the second contact section are shifted in the second direction, respectively. 
 
     
     
       2. A semiconductor device according to the  claim 1 ,
 wherein the first impurity region is shared between the first memory cell and the second memory cell. 
 
     
     
       3. A semiconductor device according to the  claim 1 ,
 wherein the second gate electrode and the fourth gate electrode are not electrically connected and are capable of being applied with a gate signal independently. 
 
     
     
       4. A semiconductor device according to the  claim 1 ,
 wherein the second gate electrode are electrically separated from the fourth gate electrode. 
 
     
     
       5. A semiconductor device according to the  claim 1 , further comprising:
 a first insulating film formed over the first memory cell and the second memory cell; 
 a first plug and a second plug formed in the first insulating film; and 
 a first wiring and a second wiring formed over the first insulating film; 
 wherein the first wiring is electrically connected to the first contact section via to the first plug, and 
 wherein the second wiring is electrically connected to the second contact section via to the second plug. 
 
     
     
       6. A semiconductor device according to the  claim 5 ,
 wherein the first wiring and the second wiring extend in the first direction. 
 
     
     
       7. A semiconductor device according to the  claim 2 ,
 wherein a first diameter of the first plug is larger than a first length of the first gate electrode in the first direction, and 
 wherein a second diameter of the second plug is larger than a second length of the second gate electrode in the first direction. 
 
     
     
       8. A semiconductor device according to the  claim 1 ,
 wherein an element isolation region is formed in the semiconductor substrate, and 
 wherein the first contact section and the second contact section are arranged over the element isolation region. 
 
     
     
       9. A semiconductor device according to the  claim 8 ,
 wherein the element isolation region is formed of a second insulating film embedded into a trench formed in the semiconductor substrate. 
 
     
     
       10. A semiconductor device according to the  claim 1 ,
 wherein silicide films are formed over the second gate electrode, the fourth gate electrode, the first contact section and the second contact section. 
 
     
     
       11. A semiconductor device according to the  claim 1 ,
 wherein the first charge storage film and the second charge storage film include a silicon nitride film, respectively. 
 
     
     
       12. A semiconductor device according to the  claim 1 ,
 wherein a length of the first gate electrode in the first direction is larger than a length of the second gate electrode in the first direction, and 
 wherein a length of the third gate electrode in the first direction is larger than a length of the fourth gate electrode in the first direction. 
 
     
     
       13. A semiconductor device according to the  claim 1 ,
 wherein a conductive film forming the second gate electrode and a conductive film forming the fourth gate electrode are not continuous with or connected with each other. 
 
     
     
       14. A semiconductor device according to the  claim 1 ,
 wherein the second gate electrode and the fourth gate electrode are physically and electrically separated from each other.