Load current sensing

Abstract

Techniques for sensing current delivered to a load by a differential output stage, e.g., in a Class D amplifier. In one aspect, voltages across sense resistors coupled in series with first and second branches of the differential output stage are low-passed filtered and digitized. The sense resistors may be coupled in series with the sources of transistors of the first and second branches, wherein the transistors are selectively switchable on and off by input voltage driving voltages. The input driving voltages may correspond to a ternary voltage waveform such that during a given phase, the two transistors coupled in series with the sense resistors may be turned off. Further aspects provide for the first and second branches having cascoded NMOS and/or PMOS transistors, and the sense resistors being provided between a pair of cascoded transistors.

The invention claimed is: 
     
       1. An apparatus comprising:
 a differential output stage comprising a first driving branch and a second driving branch, each of the first and second driving branches coupled to positive and negative voltage supply nodes; 
 a first sense resistor coupled in series with the first driving branch and the voltage supply nodes, the voltage across the first sense resistor corresponding to a first sense voltage; 
 a second sense resistor coupled in series with the second driving branch and the voltage supply nodes, the voltage across the second sense resistor corresponding to a second sense voltage; and 
 a low-pass filter configured to filter the continuous-time difference between the first and second sense voltages. 
 
     
     
       2. The apparatus of  claim 1 , further comprising an analog-to-digital converter (ADC) coupled to the output of the low-pass filter. 
     
     
       3. The apparatus of  claim 1 , further comprising a load, the first and second driving branches configured to drive the load. 
     
     
       4. The apparatus of  claim 1 , the first and second driving branches being driven by first and second input voltages, respectively, such that:
 during a first phase (I), the first input voltage is high and the second input voltage is low; 
 during a second phase (II), the first and second input voltages are high; 
 during a third phase (III), the first input voltage is low and the second input voltage is high; and 
 during a fourth phase (IV), the first and second input voltages are low. 
 
     
     
       5. The apparatus of  claim 4 , wherein each of the phases are equal in duration. 
     
     
       6. The apparatus of  claim 1 , each of the first driving branch and the second driving branch comprising an NMOS transistor and PMOS transistor coupled as an inverter, the first and second sense resistors coupled to the sources of the NMOS transistors. 
     
     
       7. The apparatus of  claim 1 , each of the first and second sense resistors comprising a poly resistor or an N+ resistor or a P+ resistor. 
     
     
       8. The apparatus of  claim 1 , each of the first and second driving branches comprising cascoded PMOS transistors and cascoded NMOS transistors, the first and second sense resistor coupled in series between the cascoded NMOS transistors. 
     
     
       9. The apparatus of  claim 1 , each of the first and second driving branches comprising cascoded PMOS transistors and cascoded NMOS transistors, the first and second sense resistor coupled in series between the cascoded PMOS transistors. 
     
     
       10. The apparatus of  claim 1 , further comprising a speaker having first and second input nodes, each of the first and second driving branches having an output node, the output nodes of the first and second driving branches coupled to the speaker first and second input nodes to drive the speaker. 
     
     
       11. The apparatus of  claim 1 , the low-pass filter comprising a differential amplifier comprising differential inputs, the differential inputs coupled to the first and second sense resistors via a resistor-capacitor (RC) network, and the differential amplifier further comprising differential outputs, the differential outputs coupled to the differential inputs via at least one switchable resistance. 
     
     
       12. The apparatus of  claim 1 , the negative voltage supply node corresponding to a ground voltage. 
     
     
       13. A method comprising:
 driving a differential output stage comprising a first driving branch and a second driving branch with first and second input voltages, respectively, each of the first and second driving branches coupled to positive and negative voltage supply nodes; and 
 low-pass filtering the continuous-time difference between voltages across first and second sense resistors, the first sense resistor coupled in series with the first driving branch and the voltage supply nodes, the second sense resistor coupled in series with the second driving branch and the voltage supply nodes. 
 
     
     
       14. The method of  claim 13 , further comprising digitizing the output of the low-pass filter. 
     
     
       15. The method of  claim 13 , the driving with first and second input voltages comprising:
 during a first phase (I), driving the first input voltage high and the second input voltage low; 
 during a second phase (II), driving the first and second input voltages high; 
 during a third phase (III), driving the first input voltage low and the second input voltage high; and 
 during a fourth phase (IV), driving the first and second input voltages low. 
 
     
     
       16. The method of  claim 13 , each of the first driving branch and the second driving branch comprising an NMOS transistor and PMOS transistor coupled as an inverter, the first and second sense resistors coupled to the sources of the NMOS transistors. 
     
     
       17. The method of  claim 13 , each of the first and second driving branches comprising cascoded PMOS transistors and cascoded NMOS transistors, the first and second sense resistor coupled in series between the cascoded NMOS transistors. 
     
     
       18. The method of  claim 13 , the negative voltage supply node corresponding to a ground voltage.