Clock feedthrough and crosstalk reduction method

Abstract

Systems and methods of the present disclosure relates generally to techniques for controlling a gate signal applied to a transistor in an electronic component. One embodiment includes decreasing a skew rate at the rising and/or falling edges of the gate signal to reduce the effects of data signal errors. Decreasing the gate signal falling edge skew rate may decrease clock feedthrough effects of the transistor, and decreasing the gate signal rising edge skew rate may decrease crosstalk effects between more than one data paths in the electronic component. The falling edge skew rate may be manipulated by initially increasing the activating voltage of the gate signal to a higher voltage, such that the gate signal may take longer to fall. The rising edge skew rate may be manipulated by increasing a voltage later during the activating period, such that the gate signal may take longer to rise.

What is claimed is: 
     
       1. An electronic system, comprising:
 gate line driving circuitry configured to:
 generate a gate clock signal; 
 generate and transmit a first gate signal to a gate of a first transistor to reduce a voltage drop of a first data signal transmitted to the first transistor, wherein generating the first gate signal comprises increasing a voltage amplitude of the first gate signal during an initial portion of an activation period of the first gate signal relative to a later portion of the activation period, and wherein the voltage amplitude of the first gate signal is increased during a single clock pulse of the gate clock signal; and 
 generate and transmit a second gate signal to a gate of a second transistor to reduce a voltage drop of a second data signal transmitted to the second transistor; 
 
 wherein the gate line driving circuitry comprises a gate signal generator, comprising:
 a first p-channel metal oxide semiconductor (PMOS) transistor configured to receive the gate clock signal, wherein the first PMOS transistor is configured to activate during the single clock pulse of the gate clock signal, and wherein the first PMOS transistor is configured to increase the voltage amplitude during the later portion of the activation period of the gate signal; 
 an n-channel metal oxide semiconductor (NMOS) transistor coupled to the first PMOS transistor and configured to receive the gate clock signal, wherein the NMOS transistor is configured to activate during an activation period of the gate clock signal; and 
 a second PMOS transistor coupled to the first PMOS transistor and the NMOS transistor, wherein the second PMOS transistor is configured to activate and increase the voltage amplitude during the initial portion of the activation period of the gate signal. 
 
 
     
     
       2. The electronic system of  claim 1 , wherein the gate line driving circuitry is configured to generate the second gate signal to increase a voltage amplitude of the second gate signal during a later portion of an activation period of the second gate signal relative to an initial portion of the activation period of the second gate signal. 
     
     
       3. The electronic system of  claim 1 , wherein the first gate signal comprises an activation period having a first voltage level and a second voltage level, wherein the first voltage level precedes the second voltage level during the activation period, and wherein the first voltage level is higher than the second voltage level. 
     
     
       4. The electronic system of  claim 3 , wherein the second gate signal comprises a post-emphasized activation period having an first voltage level and a second voltage level, wherein the first voltage level precedes the second voltage level during the activation period, and wherein the first voltage level is lower than the second voltage level. 
     
     
       5. The electronic system of  claim 4 , wherein the gate line driving circuitry is configured to generate the second gate signal to reduce a coupling effect between the first data signal and the second data signal as compared to a coupling effect when a gate signal not comprising the post-emphasized activation period is driven to the second transistor. 
     
     
       6. A display system comprising:
 a matrix of pixels, each of the pixels comprising a transistor; 
 gate line driving circuitry configured to transmit a gate signal to a gate of the transistor of each of the pixels, wherein the gate line driving circuitry comprises:
 a gate signal generator configured to:
 receive a pulsed clock signal comprising a plurality of clock pulses; 
 generate the gate signal to correspond at least in part to the pulsed clock signal; and 
 increase a voltage amplitude of the gate signal during at least one of an initial portion of a logically high period of the gate signal and a later portion of the logically high period of the gate signal, wherein increasing the voltage amplitude comprises increasing the voltage amplitude during each single clock pulse of the plurality of clock pulses of the pulsed clock signal; and 
 
 
 data line driving circuitry configured to transmit a data signal to a source of the transistor of each of the pixels, wherein increasing the voltage amplitude during the at least one of the initial portion of the logically high period and the later portion of the logically high period comprises reducing a voltage drop of the data signal across the transistor; 
 wherein the gate signal generator comprises:
 a first transistor comprising a first polarity channel and configured to receive the pulsed clock signal, wherein the first transistor is configured to activate during each single clock pulse of the plurality of clock pulses, and wherein the first transistor is configured to increase the voltage amplitude during the later portion of the logically high period of the gate signal; 
 a second transistor comprising a second polarity channel and configured to receive the pulsed clock signal, wherein the second transistor is configured to activate during a plurality of activation periods of the pulsed clock signal; and 
 a third transistor comprising a polarity channel corresponding to the first polarity channel and configured to receive a second pulsed signal, wherein the third transistor is configured to activate during clock pulses of the second pulsed signal, and wherein the third transistor is configured to increase the voltage amplitude during the initial portion of the logically high period of the gate signal. 
 
 
     
     
       7. The display system of  claim 6 , wherein the gate signal generator is configured to increase the voltage amplitude during the initial portion of the logically high period to control a clock feedthrough effect of the transistor. 
     
     
       8. The display system of  claim 6 , wherein the gate signal generator is configured to increase the voltage amplitude during the later portion of the logically high period to control a crosstalk effect of the transistor. 
     
     
       9. The display system of  claim 6 , wherein the gate signal generator is configured to select one or more voltages to generate the gate signal, wherein the one or more voltages comprises:
 a first voltage; 
 a second voltage less than the first voltage; and 
 a third voltage less than the second voltage. 
 
     
     
       10. The display system of  claim 9 , wherein the gate signal generator is configured to output a pre-emphasized signal to reduce the voltage drop of the data signal across the transistor, wherein the pre-emphasized signal comprises the first voltage followed by the second voltage followed by the third voltage. 
     
     
       11. The display system of  claim 9 , wherein the gate signal generator is configured to output a post-emphasized signal to reduce the voltage drop of the data signal across the transistor, wherein the post-emphasized signal comprises the second voltage followed by the first voltage followed by the third voltage. 
     
     
       12. A display system comprising:
 a matrix of pixels, each of the pixels comprising a transistor; 
 gate line driving circuitry configured to transmit a gate signal to a gate of the transistor of each of the pixels, wherein the gate line driving circuitry comprises:
 a gate signal generator configured to:
 receive a pulsed clock signal comprising a plurality of clock pulses; 
 generate the gate signal to correspond at least in part to the pulsed clock signal; and 
 increase a voltage amplitude of the gate signal during at least one of an initial portion of a logically high period of the gate signal and a later portion of the logically high period of the gate signal, wherein increasing the voltage amplitude comprises increasing the voltage amplitude during each single clock pulse of the plurality of clock pulses of the pulsed clock signal; and 
 
 data line driving circuitry configured to transmit a data signal to a source of the transistor of each of the pixels, wherein increasing the voltage amplitude during the at least one of the initial portion of the logically high period and the later portion of the logically high period comprises reducing a voltage drop of the data signal across the transistor; 
 wherein the gate signal generator comprises:
 a voltage selection device configured to select at least one of a plurality of received voltage levels, wherein the plurality of received voltage levels comprises a first voltage level corresponding to the voltage amplitude increase of the gate signal during the initial portion of the logically high period of the gate signal and a second voltage level corresponding to the voltage amplitude increase of the gate signal during the later portion of the logically high period of the gate signal; and 
 an amplifier coupled to the voltage selection device, wherein the amplifier is configured to output the gate signal comprising at least the first voltage level and the second voltage level.