Pipelined continuous-time sigma delta modulator

Abstract

Traditionally, pipelined continuous-time (CT) sigma-delta modulators (SDM) have been difficult to build due at least in part to the difficulties in calibrating the pipeline. Here, however, a pipelined CT SDM is provided that has an architecture that is conducing to being calibrated. Namely, the system includes a digital filter and other features that can be adjusted to account for input imbalance errors and well as quantization leakage noise.

The invention claimed is: 
     
       1. An apparatus comprising:
 a terminal; 
 an analog-to-digital converter (ADC) that is coupled to the terminal; 
 a first digital-to-analog converter (DAC) that is coupled to the ADC; 
 a first summing circuit that that is coupled to terminal and the first DAC, wherein the second summing circuit is configured to determine a difference; 
 a first gain circuit that is coupled to the first summing circuit summing circuit, wherein the first gain circuit has a first gain; 
 a continuous-time (CT) sigma-delta modulator (SDM) having:
 a second summing circuit that is coupled to the first gain circuit, wherein the second summing circuit is configured to determine a difference; 
 an SDM filter that is coupled to the second summing circuit; 
 a quantizer that is coupled to the SDM filter; and 
 a second DAC that is coupled between the quantizer and the second summing circuit; 
 
 a second gain circuit that is coupled to the second quantizer, wherein the second gain circuit has a second gain, and wherein the second gain is substantially the inverse of the first gain, and wherein the first gain circuit, the CT SDM, and the DAC collectively have a first transfer function; 
 a filter that is coupled to the ADC and second gain circuit, wherein the digital filter has a second transfer function, wherein the second transfer function substantially matches the first transfer function, 
 wherein the first DAC has a third gain, and wherein the second DAC has a fourth gain, and wherein the filter has a fifth gain, and wherein the ratio of the third gain to the fourth gain is approximately equal to the fifth gain. 
 
     
     
       2. The apparatus of  claim 1 , wherein the filter further comprises:
 a digital filter that is coupled to the ADC; 
 a third summing circuit that is coupled to the digital filter and the second gain circuit; and 
 an output circuit that is coupled to the third summing circuit. 
 
     
     
       3. The apparatus of  claim 1 , wherein the first gain circuit further comprises an amplifier with a filter. 
     
     
       4. The apparatus of  claim 1 , wherein the CT SDM further comprises a first CT SDM, and wherein the ADC further comprises a second CT SDM. 
     
     
       5. The apparatus of  claim 4 , wherein the SDM filter and quantizer further comprise a first SDM filter and a first quantizer, and wherein the second CT SDM further comprises:
 a third summing circuit that is coupled to the terminal, wherein the third summing circuit is configured to determine a difference; 
 a second SDM filter that is coupled to the third summing circuit; 
 a second quantizer that is coupled to the second SDM filter; and 
 a third DAC that is coupled between the second quantizer and the third summing circuit. 
 
     
     
       6. The apparatus of  claim 5 , wherein the apparatus further comprises a third gain circuit that is coupled between terminal and the first summing circuit. 
     
     
       7. An apparatus comprising:
 a terminal; 
 an ADC that is coupled to the terminal; 
 a first DAC that is coupled to the ADC; 
 a first gain circuit that is coupled to the terminal; 
 a first summing circuit that that is coupled to first gain circuit and the first DAC, wherein the second summing circuit is configured to determine a difference; 
 a second gain circuit that is coupled to the first summing circuit summing circuit, wherein the first gain circuit has a second gain; 
 a CT SDM having:
 a second summing circuit that is coupled to the second gain circuit, wherein the second summing circuit is configured to determine a difference; 
 an SDM filter that is coupled to the second summing circuit; 
 a quantizer that is coupled to the SDM filter; and 
 a second DAC that is coupled between the quantizer and the second summing circuit, wherein the second DAC has a third gain; 
 
 a third gain circuit that is coupled to the second quantizer, wherein the second gain circuit has a fourth gain, and wherein the fourth gain is substantially the inverse of the second gain, and wherein the second gain circuit, the CT SDM, and the DAC collectively have a first transfer function; 
 a filter that is coupled to the ADC and third gain circuit, wherein the digital filter has a second transfer function and a fifth gain, wherein the second transfer function substantially matches the first transfer function. 
 
     
     
       8. The apparatus of  claim 7 , wherein the first DAC has a third gain, and wherein the second DAC has a fourth gain, and wherein the filter has a fifth gain, and wherein the ratio of the third gain to the fourth gain is approximately equal to the fifth gain. 
     
     
       9. The apparatus of  claim 7 , wherein the filter further comprises:
 a digital filter that is coupled to the ADC; 
 a third summing circuit that is coupled to the digital filter and the second gain circuit; and 
 an output circuit that is coupled to the third summing circuit. 
 
     
     
       10. The apparatus of  claim 7 , wherein the first and second gain circuits further first and second amplifiers, respectively. 
     
     
       11. The apparatus of  claim 9 , wherein the CT SDM further comprises a first CT SDM, and wherein the ADC further comprises a second CT SDM. 
     
     
       12. The apparatus of  claim 11 , wherein the SDM filter and quantizer further comprise a first SDM filter and a first quantizer, and wherein the second CT SDM further comprises:
 a third summing circuit that is coupled to the terminal, wherein the third summing circuit is configured to determine a difference; 
 a second SDM filter that is coupled to the third summing circuit; 
 a second quantizer that is coupled to the second SDM filter; and 
 a third DAC that is coupled between the second quantizer and the third summing circuit. 
 
     
     
       13. An apparatus comprising:
 a terminal; 
 an ADC that is coupled to the terminal; 
 a predictor that is coupled to the ADC; 
 a first DAC that is coupled to the ADC; 
 a first summing circuit that that is coupled to terminal and the first DAC, wherein the second summing circuit is configured to determine a difference; 
 a first gain circuit that is coupled to the first summing circuit summing circuit, wherein the first gain circuit has a first gain; 
 a CT SDM having:
 a second summing circuit that is coupled to the first gain circuit, wherein the second summing circuit is configured to determine a difference; 
 an SDM filter that is coupled to the second summing circuit; 
 a quantizer that is coupled to the SDM filter; and 
 a second DAC that is coupled between the quantizer and the second summing circuit; 
 
 a second gain circuit that is coupled to the second quantizer, wherein the second gain circuit has a second gain, and wherein the second gain is substantially the inverse of the first gain, and wherein the first gain circuit, the CT SDM, and the DAC collectively have a first transfer function; 
 a filter that is coupled to the ADC and second gain circuit, wherein the digital filter has a second transfer function, wherein the second transfer function substantially matches the first transfer function. 
 
     
     
       14. The apparatus of  claim 13 , wherein the filter further comprises:
 a digital filter that is coupled to the ADC; 
 a third summing circuit that is coupled to the digital filter and the second gain circuit; and 
 an output circuit that is coupled to the third summing circuit. 
 
     
     
       15. The apparatus of  claim 13 , wherein the predictor further comprises an analog predictor that is coupled between the terminal and the ADC. 
     
     
       16. The apparatus of  claim 13 , wherein the predictor further comprises a digital predictor that is coupled between the ADC and the first DAC, and wherein the apparatus further comprises a delay line that is coupled between the terminal and the first summing circuit. 
     
     
       17. The apparatus of  claim 13 , wherein the CT SDM further comprises a first CT SDM, and wherein the ADC further comprises a second CT SDM. 
     
     
       18. The apparatus of  claim 17 , wherein the SDM filter and quantizer further comprise a first SDM filter and a first quantizer, and wherein the second CT SDM further comprises:
 a third summing circuit that is coupled to the terminal, wherein the third summing circuit is configured to determine a difference; 
 a second SDM filter that is coupled to the third summing circuit; 
 a second quantizer that is coupled to the second SDM filter; and 
 a third DAC that is coupled between the second quantizer and the third summing circuit. 
 
     
     
       19. The apparatus of  claim 13 , wherein the apparatus further comprises a third gain circuit that is coupled between terminal and the first summing circuit.