Semiconductor device and a method of manufacturing the same

Abstract

In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.

What is claimed is: 
     
       1. A semiconductor device comprising:
 (a) a semiconductor substrate; 
 (b) a capacitor element formed over the substrate, 
 the capacitor element (b) including: 
 (b1) a lower electrode formed over the substrate, 
 (b2) a capacitor insulating film formed over the lower electrode, and 
 (b3) an upper electrode formed over the capacitor insulating film, 
 wherein the upper electrode has a first electrode portion, a second electrode portion and a third electrode portion, 
 wherein the first electrode portion is formed so as to extend in a first direction along a surface of the semiconductor substrate, 
 wherein the second electrode portion is formed so as to extend along a direction perpendicular to the surface of the semiconductor substrate, and 
 wherein the third electrode portion is formed above the lower electrode and extends in the first direction; 
 (c) a plurality of first metal silicide portions formed at a surface of the upper electrode, 
 wherein the plurality of first metal silicide portions include a first silicide portion of the third electrode portion and a second silicide portion of the first electrode portion; and 
 (d) between the first silicide portion and the second silicide portion, a first insulating film formed over the upper electrode, 
 wherein the first insulating film extends along a surface of the third electrode portion in the first direction and covers a part of the third electrode portion, 
 wherein a length of the upper electrode in the first direction is larger than that of the lower electrode in the first direction, a length of the upper electrode in a second direction along the surface of the semiconductor substrate and intersecting the first direction is smaller than that of the lower electrode in the second direction, and 
 wherein electrical connections to the upper and lower electrodes are made only at longitudinal end portions of the upper and lower electrodes where the upper and lower electrodes are not overlapped with each other in plan view. 
 
     
     
       2. A semiconductor device according to  claim 1 ,
 wherein a first plug is formed over the second silicide portion, and 
 wherein the first plug is electrically coupled to the upper electrode. 
 
     
     
       3. A semiconductor device according to  claim 2 ,
 wherein a second metal silicide portion which does not overlap the upper electrode in plan view is formed at a surface of the lower electrode, 
 wherein, between the first silicide portion and the second metal silicide portion, the first insulating film is formed, and 
 wherein the first insulating film extends along a surface of the upper electrode in the second direction and covers at least a part of the upper electrode. 
 
     
     
       4. A semiconductor device according to  claim 3 ,
 wherein a second plug is formed over the second metal silicide portion, and 
 wherein the second plug is electrically coupled to the lower electrode. 
 
     
     
       5. A semiconductor device according to  claim 4 ,
 wherein an interlayer insulating film is formed over the capacitor element, 
 wherein the first plug and the second plug are formed in the interlayer insulating film, and 
 wherein, right over a region where the upper electrode and the lower electrode overlap each other in plan view, only the interlayer insulating film is formed. 
 
     
     
       6. A semiconductor device according to  claim 1 ,
 wherein an element isolation region is formed over the semiconductor substrate; 
 wherein the entire lower electrode and the entire upper electrode are formed over the element isolation region. 
 
     
     
       7. A semiconductor device according to  claim 1 ,
 wherein, in plan view, the capacitor element is formed in an overlapping region of the upper and lower electrodes. 
 
     
     
       8. A semiconductor device according to  claim 1 ,
 wherein the first insulating film covers the second electrode portion and a part of the third electrode portion. 
 
     
     
       9. A semiconductor device according to  claim 1 ,
 wherein a second metal silicide portion which does not overlap the upper electrode in plan view is formed at a surface of the lower electrode, 
 wherein, between the first silicide portion and the second metal silicide portion, the first insulating film is formed, and 
 wherein the first insulating film extends along an upper surface of the upper electrode and a sidewall of the upper electrode in the second direction and covers at least a part of the upper surface of the upper electrode and the sidewall of the upper electrode in continuous manner in the second direction. 
 
     
     
       10. A semiconductor device according to  claim 9 ,
 wherein a plug is formed over the second metal silicide portion, and 
 wherein the plug is electrically coupled to the lower electrode. 
 
     
     
       11. A semiconductor device according to  claim 1 ,
 wherein the first electrode portion is not overlapped with the first silicide portion in plan view. 
 
     
     
       12. A semiconductor device according to  claim 1 ,
 wherein the first insulating film covers a portion of the capacitor insulating film formed so as to extend along the direction perpendicular to the surface of the semiconductor substrate. 
 
     
     
       13. A semiconductor device according to  claim 1 ,
 wherein the upper electrode has opposite longitudinal end portions that do not overlap with the lower electrode in plan view, and the lower electrode has opposite longitudinal end portions that do not overlap with the upper electrode in plan view. 
 
     
     
       14. A semiconductor device according to  claim 13 ,
 wherein the electrical connections to the upper electrode include plug connections to upper surfaces of the opposite longitudinal end portions of the upper electrode, and the electrical connections to the lower electrode include plug connections to upper surfaces of the opposite longitudinal end portions of the lower electrode. 
 
     
     
       15. A semiconductor device according to  claim 13 ,
 wherein a second metal silicide portion is formed to have silicide portions at upper surfaces of the opposite longitudinal end portions of the lower electrode, and respective plugs are formed over the silicide portions of the second metal silicide portion so as to contact the silicide portions of the second metal silicide portion and thereby make electrical connections to the lower electrode.