Integrated circuit chip and fabrication method

Abstract

An electrical connection structure for an integrated circuit chip includes a through via provided in a opening and a laterally adjacent void that are formed in a rear face of a substrate die. A front face of the substrate die includes integrated circuits and a layer incorporating a front electrical interconnect network. The via extends through the substrate die to reach a connection portion of the front electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via above the void. A local external protection layer may at least partly cover the electrical connection via and the electrical connection pillar.

What is claimed is: 
     
       1. A method, comprising:
 producing at least one electrical connection via made of an electrically conductive material passing through a semiconductor substrate die and linked to a connection portion of a front electrical interconnect network in a layer on a front face of the semiconductor substrate die, wherein producing said electrical connection via comprises embedding the electrically conductive material in both a through hole extending through the semiconductor substrate die and a rear void extending into the semiconductor substrate die adjacent to the through hole, wherein the rear void is open out vertically only towards a rear face of the semiconductor substrate die and is further open out laterally into the through hole; 
 producing an electrical connection pillar made of an electrically conductive material placed on a rear part of the electrical connection via and positioned vertically aligned over the rear void; and 
 producing an external protection layer at least partly covering the electrical connection via and the electrical connection pillar. 
 
     
     
       2. The method according to  claim 1 , wherein the electrically conductive material is copper and the external protection layer is an alloy of cobalt (Co), tungsten (W) and phosphorous (P). 
     
     
       3. The method according to  claim 1 , wherein producing said electrical connection via comprises:
 producing said through hole extending through the semiconductor substrate die via the rear face of the semiconductor substrate die; 
 producing said void in the semiconductor substrate which is open out vertically only towards the rear face and is further open out laterally into the through hole; and 
 filling the hole and void with the electrically conductive material which is insulated from the semiconductor substrate die. 
 
     
     
       4. The method according to  claim 3 , wherein producing the electrical connection pillar comprises forming the electrical connection pillar at a location vertically aligned over the void which is filled with the electrically conductive material. 
     
     
       5. The method according to  claim 4 , wherein producing the local external protection layer at least partly covering the electrical connection via and the rear electrical connection pillar comprises performing selective chemical deposition of the protection layer. 
     
     
       6. The method according to  claim 5 , wherein the electrically conductive material is copper and the external protection layer is an alloy of cobalt (Co), tungsten (W) and phosphorous (P). 
     
     
       7. A method, comprising:
 producing a through hole extending through a semiconductor substrate die via a rear face to reveal a connection portion of a front electrical interconnect network formed in a layer on a front face of the semiconductor substrate die; 
 producing a void in the rear face of the semiconductor substrate die adjacent to the through hole which is open out vertically only towards the rear face and is further open out laterally into the through hole; 
 producing, by a physical vapor phase deposition, a thin layer made of an electrically conductive material on the rear face of the semiconductor substrate die and on the walls of the through hole and on walls of the void and on a floor of the void; 
 producing, by a local electrochemical deposition with electrical contact on said thin layer, a thick layer made of an electrically conductive material on the thin layer, in the through hole and in the void and above the rear face of the semiconductor substrate die; 
 producing, by a local electrochemical deposition with electrical contact on said thin layer, a rear electrical connection pillar on the thick layer vertically aligned above the floor of the void; and 
 removing a portion of the thin layer and the thick layer, a remaining portion of the thin layer and the thick layer after said removing forming an embedded electrical connection via linked to said front interconnect network and provided with the rear electrical connection pillar. 
 
     
     
       8. The method according to  claim 7 , further comprising, before producing the electrical connection pillar:
 removing a rear part of the thick layer in such a way that this thick layer has a rear face in a plane of the rear face of the thin layer, the electrical connection pillar being produced on this rear face of the thick layer. 
 
     
     
       9. The method according to  claim 7 , further comprising:
 producing, by a selective chemical deposition, an external protection layer at least partly covering the electrical connection via and the rear electrical connection pillar. 
 
     
     
       10. The method according to  claim 9 , wherein the electrically conductive material is copper and the external protection layer is an alloy of cobalt (Co), tungsten (W) and phosphorous (P). 
     
     
       11. The method according to  claim 7 , further comprising, before producing the thin layer:
 producing an insulating layer on the rear face of the substrate die and against the walls of the through hole and of the void; and 
 removing a part of the insulating layer situated above said connection portion of the front electrical interconnect network. 
 
     
     
       12. The method according to  claim 11 , wherein producing the insulating layer comprises performing a sub-atmospheric chemical vapor phase deposition (SACVD). 
     
     
       13. The method according to  claim 7 , wherein producing the through hole comprises performing a partial etching of the through hole and wherein producing the void comprises performing a complete etching of the through hole at the same time as an etching of the void. 
     
     
       14. An integrated circuit chip, comprising:
 a semiconductor substrate die; 
 integrated circuits on a front face of the semiconductor substrate die; 
 a front layer incorporating a front electrical interconnect network on the front face of the semiconductor substrate die; 
 a through hole extending into a rear face of the semiconductor substrate die; 
 a void adjacent to the through hole also extending into the rear face of the semiconductor substrate die, wherein the void is open out vertically only towards the rear face and open out laterally into the through hole; and 
 at least one rear electrical connection structure comprising:
 an electrical connection via in the through hole and in the void of the semiconductor substrate die and linked to a connection portion of said front electrical interconnect network; and 
 an electrical connection pillar on a rear face of the electrical connection via at a position vertically aligned above the void. 
 
 
     
     
       15. The chip according to  claim 14 , comprising a rear protection layer at least partly covering the electrical connection via and the electrical connection pillar. 
     
     
       16. The chip according to  claim 15 , wherein the electrical connection via and the electrical connection pillar comprise copper (Cu) and the rear protection layer comprises an alloy of cobalt (Co), tungsten (W) and phosphorous (P). 
     
     
       17. The chip according to  claim 14 , further including a drop of solder on an end of the pillar.