Multiple switch power stage control tracking PCM signal input

Abstract

A DC power stage provides a power output that tracks a PCM signal input. A mapping unit generates an integer number of N digital PWM signals each switched at a same switching frequency by switching states of the PWM signals one at a time based on a level of the PCM signal input. An imbalance correction unit adjusts a duty ratio of the PWM signals relative to one another based on differentially accumulating errors among the PWM signals to prevent divergence of PWM signals. N corresponding switches therefrom switch power from a DC power source. N inductances in parallel produce a combined signal that is low pass filtered to provide the power output. Switching is between only those state combinations where the switching frequency is cancelled in the combined signal. The switching frequency is a sampling frequency of the PCM signal input divided by a product of 2 times N.

What is claimed is: 
     
       1. A DC power stage for providing a power output that tracks a PCM signal input, comprising:
 a mapping unit for generating an integer number of N digital PWM signals each switched at a same switching frequency by switching states of the N digital PWM signals one at a time based on a level of the PCM signal input; 
 an imbalance correction unit operatively coupled to the mapping unit to adjust a duty ratio of the N digital PWM signals relative to one another based on differentially accumulating errors among the N digital PWM signals to prevent divergence of N digital PWM signals and produce N balanced digital PWM signals; 
 N switches each operatively coupled to a corresponding one of the N digital balanced PWM signals from the imbalance correction unit to switch power from a DC power source based on the corresponding one of N balanced digital PWM signals; 
 N inductances in parallel, each of the N inductances operatively coupled to a corresponding one of the N switches to produce a combined signal; and 
 a low pass filter operatively coupled to filter the combined signal from the N inductors and provide the power output tracking the PCM signal input. 
 
     
     
       2. A DC power stage according to  claim 1 , wherein the switching of the mapping unit is limited to switching between only those state combinations of the N digital PWM signals such that the switching frequency is cancelled in the combined signal from the N inductances. 
     
     
       3. A DC power stage according to  claim 1 ,
 wherein the PCM signal input arrives at a sampling frequency; and 
 wherein the mapping unit switches each of the N digital PWM signals at the switching frequency that is the sampling frequency of the PCM signal input divided by a product of 2 times the integer number N. 
 
     
     
       4. A DC power stage according to  claim 3 , wherein the switching of the mapping unit is limited to switching between only those state combinations of the N digital PWM signals such that the switching frequency is cancelled in the combined signal from the N inductances. 
     
     
       5. A DC power stage according to  claim 1 , wherein each of the N inductances have essentially a same inductance value so that the N balanced digital PWM signals are each essentially the same magnitude. 
     
     
       6. A DC power stage according to  claim 1 , wherein the mapping unit switches such that a center of the pulses of the N digital PWM signals are equally spaced from one another. 
     
     
       7. A DC power stage according to  claim 1 , wherein the mapping unit switches signal transitions in symmetrical patterns time offset by like phase differences between the N digital PWM signals. 
     
     
       8. A DC power stage according to  claim 1 , wherein the mapping unit switches signal transitions in like patterns with common states. 
     
     
       9. A DC power stage according to  claim 1 , wherein the mapping unit switches the N digital PWM signals in the integer number N of transitions between N plus 1 layers of 2 N  states. 
     
     
       10. A DC power stage according to  claim 9 , wherein the transitions alternate between layers. 
     
     
       11. A DC power stage according to  claim 9 , wherein every other transition returns to an adjacent state on a same layer within one of N ranges of values of the N digital PCM signals. 
     
     
       12. A DC power stage apparatus according to  claim 1 , wherein the integer number N is 2. 
     
     
       13. A DC power stage apparatus according to  claim 1 , wherein the integer number N is 3. 
     
     
       14. A DC power stage apparatus according to  claim 1 , wherein the integer number N is 4. 
     
     
       15. A two-stage DC power stage for providing a power output that tracks a PCM signal input having a sampling frequency, comprising:
 a mapping unit for generating a first digital PWM signal and a second digital PWM signal each switched at a same switching frequency by switching states of the first digital PWM signal and the second digital PWM signal one at a time based on a level of the PCM signal input; 
 an imbalance correction unit operatively coupled to the mapping unit to adjust a duty ratio of the first and second digital PWM signals relative to one another based on differential accumulation of an error between the first and second digital PWM signals to prevent divergence of the first and second digital PWM signals and produce first and second balanced digital PWM signals; 
 a two stage switch consisting of essentially no more than two switches, each of the two switches operatively coupled to a corresponding one of the first and second balanced PWM signals from the imbalance correction unit to switch power from a DC power source based on the corresponding one of the first and second balanced digital PWM signals; 
 two inductances in parallel, each of the two inductances operatively coupled to a corresponding one of the two switches to produce a combined signal; and 
 a low pass filter operatively coupled to filter the combined signal from the N inductors and provide the power output tracking the PCM signal input; and 
 wherein the mapping unit switches each of the first and second digital PWM signals at the switching frequency that is one-quarter of the sampling frequency of the PCM signal input. 
 
     
     
       16. A two-stage DC power stage according to  claim 15 , wherein the switching of the mapping unit is limited to switching between only those state combinations of the first and second digital PWM signals such that the switching frequency is cancelled in the combined signal from the two inductances. 
     
     
       17. A method of providing a power output that tracks a PCM signal input, comprising the steps of:
 (a) generating an integer number of N digital PWM signals each switched at a same switching frequency by switching states of the N digital PWM signals one at a time based on a level of the PCM signal input; 
 (b) adjusting a duty ratio of the N digital PWM signals relative to one another based on differentially accumulating errors among the N digital PWM signals to prevent divergence of N digital PWM signals and produce N balanced digital PWM signals; 
 (c) switching the N digital balanced PWM signals adjusted in said step (b) to switch power from a DC power source based on corresponding ones of N digital balanced PWM signals; 
 (d) inductively combining in parallel each of the signals switched in said step (c); and 
 (e) low pass filtering the combined signal inductively combined in said step (d) to provide the power output tracking the PCM signal input. 
 
     
     
       18. A method according to  claim 17 , wherein the switching of the N digital PWM signals generated in said step (a) is limited to switching between only those state combinations of the N digital PWM signals such that the switching frequency is cancelled in the combined signal from the N inductances. 
     
     
       19. A method according to  claim 17 ,
 wherein the PCM signal input arrives at a sampling frequency; and 
 wherein the switching of the N digital PWM signals generated in said step (a) switches each of the N digital PWM signals at the switching frequency that is the sampling frequency of the PCM signal input divided by a product of 2 times the integer number N. 
 
     
     
       20. A method according to  claim 19 , wherein the switching of the N digital PWM signals generated in said step (a) is limited to switching between only those state combinations of the N digital PWM signals such that the switching frequency is cancelled in the combined signal from the N inductances.