Nonvolatile memory device and related read method using hard and soft decision decoding

Abstract

A storage device comprises a nonvolatile memory device comprising a plurality of memory cells, and an error correction circuit configured to receive primary data and secondary data from the nonvolatile memory device and to perform a hard decision decoding operation on the primary data and further configured to perform a soft decision decoding operation on the primary data based on the secondary data. The primary data is read from the plurality of memory cells in a hard decision read operation and the secondary data is read from memory cells programmed to a specific state from among the primary data.

What is claimed is: 
     
       1. A storage device comprising:
 a nonvolatile memory device comprising a plurality of memory cells, wherein the plurality of memory cells are multi-level cells; and 
 an error correction circuit configured to receive primary data and secondary data from the nonvolatile memory device and to perform a hard decision decoding operation on the primary data and further configured to perform a soft decision decoding operation on the primary data based on the secondary data, 
 wherein the primary data is read from the plurality of memory cells in a hard decision read operation and the secondary data is read from the plurality of memory cells using a read voltage corresponding to a designated state of the plurality of memory cells, and wherein the secondary data is derived from the primary data in the hard decision read operation. 
 
     
     
       2. The storage device of  claim 1 , wherein the designated state is an erase state of the plurality of memory cells. 
     
     
       3. The storage device of  claim 2 , wherein the primary data is most significant bit (MSB) data read from the plurality of memory cells in the hard decision read operation, and a bit of the secondary data having a logical value of ‘1’ indicates that a corresponding one of the plurality of memory cells has the erase state. 
     
     
       4. The storage device of  claim 1 , wherein the designated state is a program state of the plurality of memory cells having a highest threshold voltage distribution. 
     
     
       5. The storage device of  claim 4 , wherein the primary data is most significant bit (MSB) data read from the plurality of memory cells in the hard decision read operation and a bit of the secondary data having a logical value of ‘0’ indicates that a corresponding one of the plurality of memory cells has the program state having the highest threshold voltage. 
     
     
       6. The storage device of  claim 1 , wherein the error correction circuit performs a primary soft decision decoding operation using the primary data before the soft decision decoding operation is performed. 
     
     
       7. The storage device of  claim 1 , wherein in the soft decision decoding operation, the error correction circuit adjusts the reliability of data read from memory cells programmed to the designated state based on the secondary data. 
     
     
       8. The storage device of  claim 7 , wherein the reliability is defined in relation to a log likelihood ratio (LLR). 
     
     
       9. The storage device of  claim 8 , wherein in the soft decision decoding operation, the error correction circuit corrects an absolute value of log likelihood of data, read from memory cells programmed to the designated state, from among the primary data according to the secondary data to be smaller than that of data read from memory cells programmed to another state. 
     
     
       10. A method of processing data read from a nonvolatile memory device comprising a plurality of memory cells that are multi-level cells, the method comprising:
 receiving primary data from the nonvolatile memory device; 
 performing a hard decision decoding operation on the primary data; 
 receiving secondary data from the nonvolatile memory device; and 
 performing a soft decision decoding operation on the primary data based on the secondary data, 
 wherein the primary data is data read from the plurality of memory cells in a hard decision read operation and the secondary data is read from the plurality of memory cells using a read voltage corresponding to a designated state of the plurality of memory cells, and wherein the secondary data is derived from the primary data in the hard decision read operation. 
 
     
     
       11. The method of  claim 10 , wherein the designated state is an erase state of the plurality of memory cells or a program state of the plurality of memory cells having a highest threshold voltage. 
     
     
       12. The method of  claim 10 , wherein performing the soft decision decoding operation on the primary data based on the secondary data comprises adjusting the reliability of data read from the plurality of memory cells programmed to the designated state among the primary data based on the secondary data. 
     
     
       13. The method of  claim 10 , further comprising performing a primary soft decision decoding operation using the primary data prior to the soft decision decoding operation. 
     
     
       14. The method of  claim 13 , further comprising performing the hard decision decoding operation using the primary data prior to the primary soft decision decoding operation. 
     
     
       15. The method of  claim 13 , wherein performing the primary soft decision decoding operation and receiving secondary data from the nonvolatile memory device are performed concurrently. 
     
     
       16. The method of  claim 14 , wherein the primary soft decision decoding operation is performed as a consequence of determining that the hard decision decoding operation has failed. 
     
     
       17. The method of  claim 13 , wherein the soft decision decoding operation is performed as a consequence of determining that the primary soft decision decoding operation has failed. 
     
     
       18. A method of reading a nonvolatile memory device, comprising:
 reading primary data from a plurality of multi level cells (MLCs) in the nonvolatile memory device; 
 performing a hard decision decoding operation on the primary data; 
 determining whether the hard decision decoding operation has failed; 
 upon determining that the hard decision decoding operation has failed, reading secondary data from the plurality of MLCs; and 
 performing a soft decision decoding operation based on the primary data and the secondary data, 
 wherein the primary data is read from the plurality of MLCs in a hard decision read operation and the secondary data is read from the plurality of MLCs using a read voltage corresponding to a designated state of the plurality of MLCs, and wherein the secondary data is derived from the primary data in the hard decision read operation. 
 
     
     
       19. The method of  claim 18 , further comprising determining whether the soft decision decoding operation has failed, and upon determining that the soft decision decoding operation has failed, performing a secondary soft decision decoding operation. 
     
     
       20. The method of  claim 18 , wherein the soft decision decoding operation is performed in consideration of reliability data of the primary data.