Thin film transistor array panel

Abstract

A manufacturing method of a thin film transistor array panel includes: simultaneously forming a gate conductor and a first electrode on a substrate, using a non-peroxide-based etchant; forming a gate insulating layer on the gate conductor and the first electrode; forming a semiconductor, a source electrode, and a drain electrode on the gate insulating layer; forming a passivation layer on the semiconductor, the source electrode, and the drain electrode; and forming a second electrode layer on the passivation layer.

What is claimed is: 
     
       1. A thin film transistor array panel comprising:
 a substrate; 
 a gate conductor comprising a lower layer disposed on the substrate and an upper layer disposed on the lower layer; 
 a first electrode disposed on the substrate; 
 a gate insulating layer disposed on the gate conductor and the first electrode; 
 a semiconductor disposed on the gate insulating layer; 
 a source electrode and a drain electrode disposed on the semiconductor; 
 a passivation layer disposed on the source electrode and the drain electrode; and 
 a second electrode disposed on the passivation layer, 
 wherein, the lower layer of the gate conductor and the first electrode are disposed directly on the same layer and comprise the same type of material, and 
 wherein the lower layer of the gate conductor and the first electrode comprise indium tin oxide (ITO) or indium zinc oxide (IZO), and 
 wherein the upper layer of the gate conductor comprises copper or a copper alloy. 
 
     
     
       2. The thin film transistor array panel of  claim 1 , wherein the first electrode is a reference electrode and the second electrode is a pixel electrode. 
     
     
       3. The thin film transistor array panel of  claim 1 , wherein:
 the first electrode covers a pixel area of a substrate; and 
 the first electrode comprises two or more connections that extend from the first electrode to a first electrode of an adjacent pixel area. 
 
     
     
       4. The thin film transistor array panel of  claim 1 , wherein the first electrode covers substantially all of a pixel area of a substrate. 
     
     
       5. A thin film transistor array panel comprising:
 a substrate; 
 a gate conductor comprising a lower layer disposed on the substrate and an upper layer disposed on the lower layer; 
 a pixel electrode disposed on the substrate; 
 a gate insulating layer disposed on the gate conductor and the pixel electrode; 
 a semiconductor disposed on the gate insulating layer; 
 a source electrode and a drain electrode disposed on the semiconductor; 
 a passivation layer disposed on the source electrode and the drain electrode; and 
 a reference electrode disposed on the passivation layer, 
 wherein, the lower layer of the gate conductor and the pixel electrode are disposed directly on the same layer and comprise the same type of material. 
 
     
     
       6. The thin film transistor array panel of  claim 5 , wherein the upper layer of the gate conductor comprises copper or a copper alloy. 
     
     
       7. The thin film transistor array panel of  claim 6 , wherein the lower layer of the gate conductor and the pixel electrode comprise indium tin oxide (ITO) or indium.