Method and apparatus for ceasing access to a portion of a flash memory when less than a number of errors correctable by an error correction code exists

Abstract

An integrated circuit including a first interface, a decoder, and a controller. The first interface is configured to (i) write encoded data in a portion of a flash memory, and (ii) read the encoded data back from the flash memory. The decoder is configured to (i) according to an error correction code, decode the encoded data read back from the flash memory, and (ii) based on the decoded data, determine a number of decoding errors corresponding to the decoded data. The controller is configured to, in response to the number of decoding errors being greater than or equal to a first threshold, cease accessing the portion of the flash memory. The first threshold is less than a number of errors correctable by the error correction code for the portion of the flash memory.

What is claimed is: 
     
       1. An integrated circuit comprising:
 a first interface configured to (i) write encoded data in a portion of a flash memory, and (ii) read the encoded data back from the flash memory; 
 a decoder configured to (i) according to an error correction code, decode the encoded data read back from the flash memory, and (ii) based on the decoded data, determine a number of decoding errors corresponding to the decoded data; and 
 a controller configured to, in response to the number of decoding errors being greater than or equal to a first threshold, cease accessing the portion of the flash memory, wherein the first threshold is less than a number of errors correctable by the error correction code for the portion of the flash memory. 
 
     
     
       2. The integrated circuit of  claim 1 , further comprising the flash memory. 
     
     
       3. The integrated circuit of  claim 1 , wherein:
 the portion of the flash memory comprises a plurality of memory cells; 
 the first interface is configured to (i) write the encoded data to the plurality of memory cells, and (ii) read the encoded data back from the plurality of memory cells; and 
 the decoder is configured to (i) decode the encoded data read back from the plurality of memory cells to provide the decoded data, and (ii) based on the decoded data, determine the number of decoding errors for the plurality of memory cells. 
 
     
     
       4. The integrated circuit of  claim 1 , further comprising:
 a second interface connected between (i) a host and (ii) the decoder and the controller; and 
 an encoder configured to (i) receive data from the host via the second interface, and (ii) based on the error correction code, encode the data received from the second interface to generate the encoded data, 
 wherein the second interface is configured to (i) receive the decoded data from the decoder, and (ii) forward the decoded data to the host. 
 
     
     
       5. The integrated circuit of  claim 1 , wherein the encoder, the first interface, and the decoder are implemented in the controller. 
     
     
       6. The integrated circuit of  claim 1 , wherein the controller is configured to, in response to the number of decoding errors being less than the first threshold, continue accessing the portion of the flash memory. 
     
     
       7. The integrated circuit of  claim 1 , wherein:
 the first threshold is based on a maximum number of errors correctable by the error correction code for a plurality of memory cells; and 
 the flash memory comprises the plurality of memory cells. 
 
     
     
       8. The integrated circuit of  claim 1 , wherein the number of decoding errors is indicated in the decoded data. 
     
     
       9. The integrated circuit of  claim 1 , wherein:
 the flash memory is configured to generate a status signal; 
 the status signal indicates whether a write operation to the portion of the flash memory failed; and 
 the first interface is configured to (i) cease accessing the portion of the flash memory if the status signal indicates the write operation failed, and (ii) continue accessing the portion of the flash memory if the status signal does not indicate the write operation failed. 
 
     
     
       10. The integrated circuit of  claim 9 , wherein the first interface is configured to (i) in response to the number of decoding errors being greater than or equal to the first threshold, cease accessing the portion of the flash memory, and (ii) in response to the number of decoding errors being less than the first threshold, continue accessing the portion of the flash memory. 
     
     
       11. A method comprising:
 writing encoded data in a portion of a flash memory; 
 reading the encoded data back from the flash memory; 
 according to an error correction code, decoding the encoded data read back from the flash memory; 
 based on the decoded data, determining a number of decoding errors corresponding to the decoded data; and 
 in response to the number of decoding errors being greater than or equal to a first threshold, ceasing access to the portion of the flash memory, wherein the first threshold is less than a number of errors correctable by the error correction code for the portion of the flash memory. 
 
     
     
       12. The method of  claim 11 , wherein:
 the writing of the encoded data, the reading of the encoding data, and the decoding of the encoded data are implemented in an integrated circuit; and 
 the integrated circuit comprises the flash memory. 
 
     
     
       13. The method of  claim 11 , comprising:
 writing the encoded data to a plurality of memory cells in the flash memory, wherein the portion of the flash memory comprises the plurality of memory cells; and 
 reading the encoded data back from the plurality of memory cells. 
 
     
     
       14. The method of  claim 13 , comprising:
 decoding the encoded data read back from the plurality of memory cells to provide the decoded data; and 
 based on the decoded data, determining the number of decoding errors for the plurality of memory cells. 
 
     
     
       15. The method of  claim 11 , further comprising:
 receiving data from a host via a second interface; 
 based on the error correction code, encoding the data received from the second interface to generate the encoded data; 
 receiving the decoded data from a decoder at the second interface; and 
 forwarding the decoded data to the host. 
 
     
     
       16. The method of  claim 15 , wherein:
 the data received from the host is encoded via an encoder; 
 the encoded data is decoded via the decoder; 
 the encoded data is written to the flash memory via an interface; 
 the number of decoding errors is determined by a controller; and 
 the encoder, the decoder, the interface and the controller are implemented in an integrated circuit. 
 
     
     
       17. The method of  claim 11 , further comprising, in response to the number of decoding errors being less than the first threshold, continuing to access the portion of the flash memory. 
     
     
       18. The method of  claim 11 , wherein:
 the first threshold is based on a maximum number of errors correctable by the error correction code for a plurality of memory cells; and 
 the flash memory comprises the plurality of memory cells. 
 
     
     
       19. The method of  claim 11 , further comprising indicating the number of decoding errors in the decoded data. 
     
     
       20. The method of  claim 11 , further comprising:
 generating a status signal via the flash memory, wherein the status signal indicates whether a write operation to the portion of the flash memory failed; 
 ceasing access to the portion of the flash memory if the status signal indicates the write operation failed; and 
 
       continuing to access the portion of the flash memory if the status signal does not indicate the write operation failed.