Semiconductor memory device including write driver and method of controlling the same

Abstract

Disclosed is a method of controlling a semiconductor memory device including a write driver. A method of controlling a phase change memory device includes turning on switches connected to a global bit line and a local bit line, respectively, enabling a write driver connected to the switches, enabling a word line, and enabling a memory cell to be accessed by the word line, wherein control is performed so that electric charges supplied from the write driver through the switches are charged when the write driver is enabled.

What is claimed is: 
     
       1. A method of controlling a semiconductor memory device, comprising:
 turning on switches connected to a global bit line and a local bit line, respectively; 
 enabling a write driver connected to the switches; 
 enabling a word line; and 
 enabling a memory cell to be accessed by the word line, 
 wherein in the turning on of switches, control is performed so that electric charges supplied from the write driver are charged by capacitors connected to the respective switches, and 
 when enabling the word line, control is performed so that an overshoot is generated by a sudden discharge of the electric charges charged in the capacitors. 
 
     
     
       2. The method according to  claim 1 , wherein control is performed so that the global bit line and the local bit line are enabled earlier than the word line by the switches. 
     
     
       3. A method of controlling a semiconductor memory device, comprising:
 enabling a write driver in response to a write command; 
 enabling a word line after enabling the write driver; and 
 enabling a memory cell to be accessed by the word line, 
 wherein the enabling of a word line comprises turning on switches connected to a global bit line and a local bit line, respectively, and 
 wherein in the turning on of switches, control is performed so that electric charges supplied from the write driver are charged by capacitors connected to the respective switches, and 
 when enabling the word line, control is performed so that an overshoot is generated by a sudden discharge of the electric charges charged in the capacitors. 
 
     
     
       4. The method according to  claim 3 , wherein when enabling the write driver, control is performed so that the global bit line and the local bit line are enabled earlier than the word line by the switches. 
     
     
       5. The method according to  claim 3 , further comprising discharging a write current supplied to the memory cell after a specific time when the word line is enabled. 
     
     
       6. A semiconductor memory device, comprising:
 a write driver configured to supply a write current in response to a write command;
 first and second switches connected to the write driver and configured to supply the write current to a memory cell in response to a global bit line control signal and a local bit line control signal; and 
 a word line controller configured to perform control so that the write current flowing through the memory cell sinks in response to a word line control signal, 
 wherein first and second switches are controlled so that electric charges supplied from the write driver are charged by first and second capacitors connected to the first and second switches, respectively, and 
 the word line controller is controlled so that an overshoot is generated by a sudden discharge of the electric charges charged in the first and second capacitors. 
 
 
     
     
       7. The semiconductor memory device according to  claim 6 , wherein:
 the first capacitor is connected to the first switch through a global bit line; and 
 the second capacitor is connected to the second switch through a local bit line. 
 
     
     
       8. The semiconductor memory device according to  claim 7 , further comprising a discharge unit connected to the global bit line. 
     
     
       9. The semiconductor memory device according to  claim 8 , wherein the discharge unit is configured for discharging the voltage of the global bit line in response to a discharge enable signal. 
     
     
       10. The semiconductor memory device according to  claim 6 , wherein the memory cell is connected to the word line controller through a word line. 
     
     
       11. The semiconductor memory device according to  claim 8 , wherein the write driver, first switch, and second switch comprise of PMOS transistors, and the discharge unit comprises a NMOS transistor.