Layout method and method of manufacturing semiconductor device

Abstract

A plurality of gate electrode patterns to be laid out in parallel are alternately set as first patterns to be formed in a first exposure step of double patterning and as second patterns to be formed in a second exposure step. Subsequently, a circuit that includes transistor pairs each formed by connecting one of the first patterns and one of the second patterns in parallel is laid out. This reduces the risk of variations in characteristics of transistors caused by double patterning.

What is claimed is: 
     
       1. A layout method performed by a computer, comprising:
 alternately setting, by the computer, a plurality of gate electrode patterns to be laid out in parallel as a first pattern to be formed in a first exposure step of double patterning and a second pattern to be formed in a second exposure step of the double patterning; and 
 laying out, by the computer, a circuit that includes a transistor pair formed from a first transistor whose gate electrode is of the first pattern and a second transistor whose gate electrode is of the second pattern and connected to the gate electrode of the first transistor via a wiring pattern, the first transistor having a first source and a first drain connected respectively to a second source and a second drain of the second transistor. 
 
     
     
       2. The layout method according to  claim 1 , wherein the gate electrode patterns are laid out such that an input signal is supplied in parallel to the gate electrode pattern set as the first pattern and that set as the second pattern in the transistor pair. 
     
     
       3. A method of manufacturing a semiconductor device using double patterning, the method comprising:
 first exposure for forming a first gate electrode pattern of a first transistor by exposure; 
 second exposure for forming a second gate electrode pattern of a second transistor by exposure, the second gate electrode pattern being laid out parallel to the first gate electrode pattern; and 
 wiring for connecting the first gate electrode pattern of the first transistor with the second gate electrode pattern of the second transistor via a wiring pattern, as well as connecting a first source and a first drain of the first transistor with a second source and a second drain of the second transistor, respectively. 
 
     
     
       4. The method according to  claim 1 , wherein the first transistor and the second transistor are both p-type transistors or both n-type transistors. 
     
     
       5. The method according to  claim 3 , wherein the first transistor and the second transistor are both p-type transistors or both n-type transistors. 
     
     
       6. A layout method performed by a computer, comprising:
 alternately setting, by the computer, a plurality of gate electrode patterns to be laid out in parallel as a first pattern to be formed in a first exposure step of double patterning and a second pattern to be formed in a second exposure step of the double patterning; and 
 laying out, by the computer, a circuit that includes a first transistor pair formed from a first transistor whose gate electrode is of the first pattern and a second transistor whose gate electrode is of the second pattern and connected to the gate electrode of the first transistor via a first wiring pattern, and includes a second transistor pair formed from a third transistor whose gate electrode is of the first pattern and a fourth transistor whose gate electrode is of the second pattern and connected to the gate electrode of the third transistor via a second wiring pattern, a first node connected to a drain of the first transistor and a drain of the second transistor, and a second node connected to a source of the third transistor and a source of the fourth transistor, the first and fourth transistors being inserted in series between the first node and the second node, the second and third transistors being inserted in series between the first node and the second node. 
 
     
     
       7. The method according to  claim 6 , wherein the first, second, third, and fourth transistors are all p-type transistors or all n-type transistors. 
     
     
       8. A semiconductor device, comprising:
 a first transistor including a first gate electrode formed in a first exposure step of double patterning, besides including a first source and a first drain; 
 a second transistor including a second gate electrode formed in a second exposure step of double patterning and laid out parallel to the first gate electrode pattern, besides including a second source and a second drain; 
 a first wiring pattern that connects the first gate electrode of the first transistor to the second gate electrode of the second transistor; 
 a second wiring pattern that connects the first source of the first transistor to the second source of the second transistor; and 
 a third wiring pattern connecting the first drain of the first transistor to the second drain of the second transistor. 
 
     
     
       9. The semiconductor device according to  claim 8 , wherein the first transistor and the second transistor are both p-type transistors or both n-type transistors. 
     
     
       10. A semiconductor device, comprising:
 a first transistor including a first gate electrode formed in a first exposure step of double patterning, besides including a first source and a first drain; 
 a second transistor including a second gate electrode formed in a second exposure step of double patterning and laid out parallel to the first gate electrode pattern, besides including a first source and a second drain; 
 a third transistor including a third gate electrode formed in the first exposure step of double patterning, besides including a third source and a third drain; 
 a fourth transistor including a fourth gate electrode formed in the second exposure step of double patterning and laid out parallel to the third gate electrode pattern, besides including a fourth source and a fourth drain; 
 a first node connected to the first drain of the first transistor and the second drain of the second transistor; and 
 a second node connected to the third source of the third transistor and the fourth source of the forth transistor, 
 wherein the first transistor and the fourth transistor are inserted in series between the first node and the second node, and the second transistor and the third transistor are inserted in series between the first node and the second node. 
 
     
     
       11. The semiconductor device according to  claim 10 , wherein the first, second, third, and fourth transistors are all p-type transistors or all n-type transistors.