US9024361B2ActiveUtilityA1

Solid-state imaging device and method of manufacturing solid-state imaging device

80
Assignee: OHRI HIROYUKIPriority: Jul 27, 2009Filed: Jul 19, 2010Granted: May 5, 2015
Est. expiryJul 27, 2029(~3.1 yrs left)· nominal 20-yr term from priority
H10F 39/014H10F 39/80H10F 39/803H10F 39/8037H01L 27/14609H01L 27/14689
80
PatentIndex Score
3
Cited by
12
References
11
Claims

Abstract

Provided is a solid-state imaging device including: a photodiode which converts an optical signal to signal charges; a transfer gate which transfers the signal charges from the photodiode; an impurity diffusion layer to which the signal charges are transferred by the transfer gate; and a MOS transistor of which a gate is connected to the impurity diffusion layer. The impurity diffusion layer has a first conduction type semiconductor layer and a second conduction type semiconductor layer which is formed in the first conduction type semiconductor layer and under an end portion of the transfer gate.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A solid-state imaging device comprising:
 a substrate; 
 a photodiode configured to convert an optical signal to signal charges; 
 a transfer gate on the substrate and configured to transfer the signal charges from the photodiode; 
 an impurity diffusion layer configured to receive the signal charges from the transfer gate; and 
 a transistor having a gate connected to the impurity diffusion layer, 
 wherein,
 the impurity diffusion layer has a first conduction type semiconductor layer and a second conduction type semiconductor layer, the first conduction type semiconductor layer and the second conduction type semiconductor layer being impurity regions of the substrate that are (a) opposite conduction types and (b) different in composition from that of the substrate, 
 the first conduction type semiconductor layer has an uppermost surface exposed at a top surface of the substrate, and 
 the second conduction type semiconductor layer overlaps the first conduction type semiconductor layer and has a portion disposed under an end portion of the transfer gate. 
 
 
     
     
       2. The solid-state imaging device according to  claim 1 , wherein the first conduction type semiconductor layer and the second conduction type semiconductor layer are in contact with each other. 
     
     
       3. The solid-state imaging device according to  claim 1 , further comprising an element isolation region, wherein the second conduction type semiconductor layer includes a portion between the element isolation region and the first conduction type semiconductor layer. 
     
     
       4. The solid-state imaging device according to  claim 1 , further comprising:
 a reset transistor; and 
 a second impurity diffusion layer including a first conduction type semiconductor layer and a second conduction type semiconductor layer, 
 wherein,
 the first conduction type semiconductor layer of the second impurity diffusion layer is a source region of the reset transistor, and 
 the second conduction type semiconductor layer of the second impurity diffusion region is under an end portion of a reset gate of the reset transistor. 
 
 
     
     
       5. The solid-state imaging device according to any one of  claims 1  to  3 , wherein:
 the solid-state imaging device includes a plurality of impurity diffusion layers and a plurality of transfer gates in one pixel, and 
 each second conduction type semiconductor layer is under the end portion of the respective transfer gate. 
 
     
     
       6. The solid-state imaging device according to  claim 5 , wherein in the at least one or more impurity diffusion layers, a surface of each first conduction type semiconductor layer is at least partially covered with the respective second conduction type semiconductor layer. 
     
     
       7. The solid-state imaging device according to  claim 1 , further comprising:
 a plurality of pixels, 
 
       wherein,
 the solid-state imaging device is of a global shutter scheme where all of the plurality of pixels simultaneously perform image capturing operations, and 
 all of the plurality of pixels simultaneously perform the transfer of signal charges from a plurality of the photodiodes to a plurality of the impurity diffusion layers so that the signal charges are stored in the plurality of the impurity diffusion layers during a time interval from the transferring to reading. 
 
     
     
       8. An electronic apparatus comprising a solid-state imaging device, said solid-state imaging device including:
 a substrate; 
 a photodiode configured to convert an optical signal to signal charges; 
 a transfer gate on the substrate and configured to transfer the signal charges from the photodiode; 
 an impurity diffusion layer configured to receive the signal charges that are transferred by the transfer gate; and 
 a transistor having a gate is connected to the impurity diffusion layer, 
 wherein,
 the impurity diffusion layer has a first conduction type semiconductor layer and a second conduction type semiconductor layer, the first conduction type semiconductor layer and the second conduction type semiconductor layer being impurity regions of the substrate that are (a) opposite conduction types and (b) different in composition from that of the substrate, 
 the first conduction type semiconductor layer has an uppermost surface exposed at a top surface of the substrate, and 
 the second conduction type semiconductor layer overlaps the first conduction type semiconductor layer and has a portion disposed under an end portion of the transfer gate. 
 
 
     
     
       9. The electronic apparatus of  claim 8 , wherein the first conduction type semiconductor layer is n-type and the second conduction type semiconductor layer is p-type. 
     
     
       10. The electronic apparatus of  claim 8 , wherein the first conduction type semiconductor layer does not overlap the end portion of the transfer gate. 
     
     
       11. The solid-state imaging device of  claim 1 , wherein the first conduction type semiconductor layer does not overlap the end portion of the transfer gate.

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