Data reading device

Abstract

There is disclosed a data reading device in which data of a nonvolatile storage element is reflected in a circuit to be regulated, with a minimum necessary delay width after turning a power on or after reset cancellation, and wrong writing due to a static electricity is prevented. A delay circuit is additionally disposed to output a delayed data reading signal after a signal of turning the power on or a signal of the reset cancellation is generated. A delay time T 2 and a static electricity convergence time T 1 are set so as to keep a relation of T 1< T 2.

What is claimed is: 
     
       1. A data reading device comprising:
 a crystal oscillation circuit which outputs a source oscillation for generation of a timing to perform data reading; 
 a frequency dividing circuit which divides a frequency of the source oscillation; 
 an oscillation stop detection circuit which detects whether the crystal oscillation circuit outputs oscillation, by use of an arbitrary frequency signal generated in the frequency dividing circuit; 
 a reading signal generation circuit which outputs a-data reading signals; 
 a delay circuit which delays the data reading signal; and 
 a data reading circuit including a nonvolatile storage element, 
 wherein the reading signal generation circuit outputs a first reading signal and a second reading signal, and into the data reading circuit where the second reading signal is delayed by the delay circuit. 
 
     
     
       2. The data reading device according to  claim 1 , wherein the reading signal generation circuit outputs the first reading signal when a signal synchronized with an arbitrary frequency is input, and outputs the second reading signal when an oscillation stop detection signal or a reset cancellation signal is input. 
     
     
       3. The data reading device according to  claim 1 ,
 wherein a delay time T 2  of the second reading signal is longer than a static electricity convergence time T 1  of an integrated circuit. 
 
     
     
       4. The data reading device according to  claim 2 ,
 wherein a delay time T 2  of the second reading signal is longer than a static electricity convergence time T 1  of an integrated circuit.