Variability and aging sensor for integrated circuits

Abstract

A ring-oscillator-based on-chip sensor (OCS) includes a substrate having a semiconductor surface upon which the OCS is formed. The OCS includes an odd number of digital logic stages formed in and on the semiconductor surface including a first stage and a last stage each including at least one NOR gate including a first gate stack and/or a NAND gate including a second gate stack. A feedback connection is from an output of the last stage to an input of the first stage. At least one discharge path including at least a first p-channel metal-oxide semiconductor (PMOS) device is coupled between the first gate stack and a ground pad, and/or at least one charge path including at least a first n-channel metal-oxide semiconductor (NMOS) device is coupled between the second gate stack a power supply pad.

The invention claimed is: 
     
       1. A ring-oscillator-based on-chip sensor (OCS), comprising:
 a substrate having a semiconductor surface upon which said OCS is formed; said OCS including:
 an odd number of digital logic stages formed in and on said semiconductor surface including:
 a first stage and a last stage each including at least one NOR gate including a first gate stack and/or a NAND gate including a second gate stack; 
 a feedback connection from an output of said last stage to an input of said first stage, and 
 at least one discharge path including at least a first p-channel metal-oxide semiconductor (PMOS) device coupled between said first gate stack and a ground pad, or at least one charge path including at least a first n-channel metal-oxide semiconductor (NMOS) device coupled between said second gate stack a power supply pad. 
 
 
 
     
     
       2. The OCS of  claim 1 , wherein said OCS includes said NOR gate, provides said discharge path, and further includes at least a second PMOS device having an enable input in series with said first PMOS device. 
     
     
       3. The OCS of  claim 1 , wherein said OCS includes said NAND gate, provides said charge path, and further includes at least a second NMOS device having an enable input in series with said first NMOS device. 
     
     
       4. The OCS of  claim 3 , wherein said OCS further includes said NOR gate, provides said discharge path, and further includes at least a second PMOS device having an enable input in series with said first PMOS device. 
     
     
       5. The OCS of  claim 1 , wherein said OCS is formed on said semiconductor surface. 
     
     
       6. The OCS of  claim 1 , wherein said at least one discharge path includes a plurality of said discharge paths electrically in parallel, and/or wherein said at least one charge path includes a plurality of said charge paths electrically in parallel. 
     
     
       7. The OCS of  claim 4 , further comprising a system on a chip (SOC) sharing said semiconductor surface with said OCS, said SOC providing a scan controlled digital bank that controls enable inputs which are coupled to at least one of said enable input of said second PMOS device and said enable input of said second NMOS device. 
     
     
       8. A system on a chip (SOC), comprising:
 a substrate having a semiconductor surface upon which said SOC is formed; said SOC including: 
 digital circuitry, analog circuitry, and mixed-signal circuitry in and on said semiconductor surface; and 
 a ring-oscillator-based on-chip sensor (OCS) in and on said semiconductor surface; including: 
 an odd number of digital logic stages formed in and on said semiconductor surface including:
 a first stage and a last stage each including at least one NOR gate including a first gate stack and/or a NAND gate including a second gate stack; 
 a feedback connection from an output of said last stage to an input of said first stage, and 
 at least one discharge path including at least a first p-channel metal-oxide semiconductor (PMOS) device coupled between said first gate stack and a ground pad, or at least one charge path including at least a first n-channel metal-oxide semiconductor (NMOS) device coupled between said second gate stack a power supply pad. 
 
 
     
     
       9. The SOC of  claim 8 , wherein said OCS includes said NOR gate, provides said discharge path, and further includes at least a second PMOS device having an enable input in series with said first PMOS device. 
     
     
       10. The SOC of  claim 8 , wherein said OCS includes said NAND gate, provides said charge path, and further includes at least a second NMOS device having an enable input in series with said first NMOS device. 
     
     
       11. The SOC of  claim 10 , wherein said OCS further includes said NOR gate, provides said discharge path, and further includes at least a second PMOS device having an enable input in series with said first PMOS device. 
     
     
       12. The SOC of  claim 8 , wherein said at least one discharge path includes a plurality of said discharge paths electrically in parallel, and/or wherein said at least one charge path includes a plurality of said charge paths electrically in parallel. 
     
     
       13. The SOC of  claim 11 , wherein said SOC provides a scan controlled digital bank that controls enable inputs which are coupled to at least one of said enable input of said second PMOS device and said enable input of said second NMOS device. 
     
     
       14. The SOC of  claim 11 , wherein said OCS, said digital circuitry, said analog circuitry, and said mixed-signal circuitry all include MOS devices having a gate stack comprising a metal gate on a high-k dielectric. 
     
     
       15. A method for adaptively scaling voltage in an integrated circuit (IC), the method comprising:
 providing a ring-oscillator-based on-chip sensor (OCS), including a substrate having a semiconductor surface upon which said OCS is formed; said OCS including an odd number of digital logic stages formed in and on said semiconductor surface including a first stage and a last stage each including at least one NOR gate including a first gate stack and/or a NAND gate including a second gate stack; a feedback connection from an output of said last stage to an input of said first stage, and at least one discharge path including at least a first p-channel metal-oxide semiconductor (PMOS) device coupled between said first gate stack and a ground pad, or at least one charge path including at least a first n-channel metal-oxide semiconductor (NMOS) device coupled between said second gate stack a power supply pad, 
 obtaining a frequency measurement from said OCS; 
 determining a change in at least one voltage selected from VDD, Vbn and Vbp for said IC from said frequency measurement. 
 
     
     
       16. The method of  claim 15 , wherein said OCS further includes said NOR gate, provides said discharge path, and further includes at least a second PMOS device having an enable input in series with said first PMOS device or a second NMOS device having an enable input in series with said first NMOS device, said method further comprising:
 using a scan controlled digital bank to control enable inputs which are coupled to at least one of said enable input of said second PMOS device and said enable input of said second NMOS device. 
 
     
     
       17. The method of  claim 15 , further comprising scanning gates of said OCS having said enable inputs with a scan code, wherein a strength of said discharge path and/or said charge path is varied through said scan code such that a V DD  of said OCS (OCS V DD ) is higher than a logic V DD  on product circuitry to be guardbanded by said OCS so as to provide a bounding guardband.