Memory cell with volatile and non-volatile storage

Abstract

The invention concerns a memory device comprising at least one memory cell comprising: first and second pairs of cross-coupled transistors; and a first resistance switching element ( 202 ) coupled between a first supply voltage (VDD, GND) and a first transistor of said first pair of transistors and programmed to have one of first and second resistances; and control circuitry adapted to store a data value (D NV ) at said first and second storage nodes by coupling said first storage node to said second supply voltage (V DD , GND), the data value being determined by the programmed resistance of the first resistance switching element.

The invention claimed is: 
     
       1. A memory device comprising:
 at least one memory cell comprising: 
 first and second pairs of transistors each pair coupled in series between first and second supply voltages, wherein a first storage node between the first pair of transistors is coupled to control terminals of the second pair of transistors, and a second storage node between the second pair of transistors is coupled to control terminals of the first pair of transistors; and 
 a first resistance switching element coupled between said first supply voltage and a first transistor of said first pair of transistors and programmed to have one of first and second resistances; 
 a fifth transistor directly coupled between said first storage node and a first access line; and 
 a sixth transistor coupled between said second storage node and a second access line, wherein said fifth transistor is controlled by a first control line and said sixth transistor is controlled by a second control line independent of the first control line. 
 
     
     
       2. The memory device of  claim 1 , further comprising:
 control circuitry adapted to store a data value at said first and second storage nodes by coupling said first storage node to said first supply voltage and then coupling said first storage node to said second supply voltage, the data value being determined by the programmed resistance of the first resistance switching element. 
 
     
     
       3. The memory device of  claim 2 , wherein said control circuitry is arranged to couple said first storage node to said first and second supply voltages by activating said fifth transistor. 
     
     
       4. The memory device of  claim 1 , wherein the at least one memory cell further comprises a second resistance switching element coupled between said first supply voltage and a first transistor of said second pair of transistors and programmed to have one of first and second resistances. 
     
     
       5. The memory device of  claim 4 , further comprising:
 control circuitry adapted to: 
 store a first data value at said first and second storage nodes by coupling said first storage node to said first supply voltage and then coupling said first storage node to said second supply voltage, the data value being determined by the programmed resistance of the first resistance switching element; and 
 store a second data value at said first and second storage nodes by coupling said second storage node to said first supply voltage, and then coupling said second storage node to said second supply voltage, the second data value being determined by the programmed resistance of the second resistance switching element. 
 
     
     
       6. The memory device of  claim 1 , wherein the at least one memory cell further comprises a further resistance switching element coupled between said second supply voltage and a second transistor of said first pair of transistors and programmed to have one of first and second resistances. 
     
     
       7. The memory device of  claim 6 , further comprising control circuitry adapted to store a further data value at said first and second storage nodes by coupling said first storage node to said first supply voltage, the data value being determined by the programmed resistance of the further resistance switching element. 
     
     
       8. The memory device of  claim 7 , wherein said control circuitry is adapted to select between storing said data value and said further data value at said first and second storage nodes by applying said first or second supply voltage to said first storage node. 
     
     
       9. The memory device of  claim 1 , wherein:
 the at least one memory cell further comprises: 
 a third resistance switching element coupled between said second supply voltage and a second transistor of said first pair of transistors and programmed to have one of said first and second resistances; and 
 a fourth resistance switching element coupled between said second supply voltage and a second transistor of said second pair of transistors and programmed to have one of said first and second resistances; and 
 control circuitry adapted to store a further data value at said first and second storage nodes by coupling said first storage node to said first supply voltage, the data value being determined by the relative resistances of the third and fourth resistance switching elements. 
 
     
     
       10. The memory device of  claim 1 , further comprising programming circuitry adapted to program the resistances of said first resistance switching element based on input data. 
     
     
       11. The memory device of  claim 1 , wherein said first resistance switching element is one of:
 an oxide resistive element; 
 a conductive bridging element; 
 a phase change element; 
 a programmable metallization element; 
 a spin-torque-transfer element; 
 a thermally assisted switching element and 
 a field-induced magnetic switching element. 
 
     
     
       12. A random access memory comprising an array of memory devices, each of the memory devices comprising the memory device of  claim 1 . 
     
     
       13. A field programmable gate array comprising at least one multiplexer comprising an input coupled to the memory device of  claim 1 . 
     
     
       14. A field programmable gate array comprising:
 a plurality of configurable logic blocks; and 
 at least one switching block adapted to interconnect said plurality of configurable logic blocks, wherein said at least one switching block comprises the memory device of  claim 1 . 
 
     
     
       15. A method of transferring a data value from non-volatile storage of a memory cell to first and second volatile storage nodes of said memory cell, wherein the memory cell comprises first and second pairs of transistors each pair coupled in series between first and second supply voltages, wherein a first storage node between the first pair of transistors is coupled to control terminals of the second pair of transistors, and a second storage node between the second pair of transistors is coupled to control terminals of the first pair of transistors; a first resistance switching element coupled between said first supply voltage and a first transistor of said first pair of transistors and programmed to have one of first and second resistances; a fifth transistor directly coupled between said first storage node and a first access line; and a sixth transistor coupled between said second storage node and a second access line, wherein said fifth transistor is controlled by a first control line and said sixth transistor is controlled by a second control line independent of the first control line, the method comprising:
 coupling said first storage node to said first supply voltage and then coupling said first storage node to said second supply voltage, the data value being determined by the programmed resistance of the first resistance switching element.