US9059317B2ActiveUtilityPatentIndex 50
Method of making an electronic device having a liquid crystal polymer solder mask laminated to an interconnect layer stack and related devices
Est. expiryJan 14, 2031(~4.5 yrs left)· nominal 20-yr term from priority
H10W 70/687H10W 90/28H10W 72/0198H10W 72/952H10W 72/29H10W 90/00H10W 72/07236H10W 72/072H10W 72/241H10W 90/722H10W 90/724H10W 72/252H10W 72/242H10W 72/01255H10W 72/01233H10W 70/685H10W 74/131H10W 72/30H10W 70/69H10W 72/073Y10T29/49144H05K 3/3436H05K 1/0306Y10T29/49165H05K 2201/10674H05K 2201/0141Y10T428/25H05K 2203/063H05K 3/281Y10T29/49156H05K 3/3452Y10T428/31721Y10T428/24917H01L 2924/00H01L 2224/131H01L 24/16H01L 2225/06513H01L 2224/16145H01L 25/0657H01L 2924/01327H01L 2224/11422H01L 24/33H01L 24/11H01L 2224/05647H01L 2224/1148H01L 2224/81H01L 23/3157H01L 2224/13599H01L 2224/05099H01L 2224/13099H01L 2225/06568H01L 23/49822H01L 2224/81191H01L 2224/05599H01L 23/49894H01L 2924/014H01L 24/13H01L 2224/16237H01L 2224/29599H01L 24/83H01L 2924/00013H01L 2224/29099H01L 2224/13021H01L 2224/0401H01L 2924/01029H01L 2924/00014H01L 2224/81815H01L 24/81H01L 24/94H01L 2224/94
50
PatentIndex Score
0
Cited by
75
References
22
Claims
Abstract
A method for making an electronic device includes forming an interconnect layer stack on a rigid wafer substrate having a plurality of patterned electrical conductor layers, a dielectric layer between adjacent patterned electrical conductor layers, and at least one solder pad on an uppermost patterned electrical conductor layer. An LCP solder mask having at least one aperture therein alignable with the at least one solder pad is formed. The LCP solder mask and interconnect layer stack are aligned and laminated together. Solder is positioned in the at least one aperture. At least one circuit component is attached to the at least one solder pad using the solder.
Claims
exact text as granted — not AI-modifiedThat which is claimed is:
1. A method of making an electronic device comprising:
forming an interconnect layer stack on a rigid wafer substrate and comprising a plurality of patterned electrical conductor layers with dielectric layers between adjacent patterned electrical conductor layers, and at least one solder pad on an uppermost patterned electrical conductor layer;
forming an LCP solder mask separate from the interconnect layer stack and having at least one aperture therein alignable with the at least one solder pad;
aligning the LCP solder mask and interconnect layer stack so that the at least one aperture is aligned with the at least one solder pad;
aligning and laminating the LCP solder mask and the interconnect layer stack together by applying heat and pressure to the LCP solder mask and the uppermost layer of the plurality of circuit layers;
positioning a conductive material in the at least one aperture by dipping the electronic device in a solder bath; and
attaching at least one circuit component to the at least one solder pad using the solder conductive material.
2. The method of claim 1 , wherein the conductive material comprises solder; and wherein attaching the at least one circuit component comprises heating the solder.
3. The method of claim 1 , wherein the conductive material comprises epoxy; and wherein attaching the at least one circuit component comprises heating the epoxy.
4. The method of claim 1 , wherein applying heat and pressure is performed in an autoclave.
5. The method of claim 1 , wherein forming the LCP solder mask comprises at least one of punching and laser milling the at least one aperture.
6. The method of claim 1 , wherein forming the interconnect layer stack comprises forming the plurality of patterned electrical conductor layers using conventional thin film deposition.
7. The method of claim 1 , wherein the at least one circuit component comprises at least one integrated circuit.
8. The method of claim 1 , wherein the LCP solder mask has a thickness of less than 0.0015 inches.
9. An electronic device comprising:
a semiconductor layer;
an interconnect layer stack on said rigid wafer substrate semiconductor layer and comprising a plurality of patterned electrical conductor layers, a dielectric layer between adjacent patterned electrical conductor layers, and at least one solder pad on an uppermost patterned electrical conductor layer;
an LCP solder mask on said interconnect layer stack and having at least one aperture aligned with said at least one solder pad;
a fused seam between said interconnect layer stack and said LCP solder mask;
a conductive material in the at least one aperture; and
at least one circuit component electrically coupled to said at least one solder pad through said solder conductive material.
10. The electronic device of claim 9 , wherein the conductive material comprises solder.
11. The electronic device of claim 9 , wherein the conductive material comprises epoxy.
12. The electronic device of claim 9 , wherein said at least one solder pad comprises a plurality thereof arranged in an array pattern.
13. The electronic device of claim 9 , wherein said at least one circuit component comprises at least one integrated circuit.
14. The electronic device of claim 9 , wherein said LCP solder mask has a thickness of less than 0.0015 inches.
15. A method of making an electronic device comprising:
forming an interconnect layer stack on a substrate and comprising a plurality of patterned electrical conductor layers with dielectric layers between adjacent patterned electrical conductor layers, and at least one solder pad on an uppermost patterned electrical conductor layer;
forming an LCP solder mask separate from the interconnect layer stack and having at least one aperture therein;
aligning the LCP solder mask and interconnect layer stack so that the at least one aperture is aligned with the at least one solder pad;
laminating the LCP solder mask and the interconnect layer stack together; and
attaching at least one circuit component to the at least one solder pad using a conductive material positioned in the at least one aperture.
16. The method of claim 15 , wherein the conductive material comprises solder; and wherein attaching the at least one circuit component comprises heating the solder.
17. The method of claim 15 , wherein the conductive material comprises epoxy; and wherein attaching the at least one circuit component comprises heating the epoxy.
18. The method of claim 15 , wherein laminating comprises applying heat and pressure in an autoclave.
19. The method of claim 15 , wherein forming the LCP solder mask comprises at least one of punching and laser milling the at least one aperture.
20. The method of claim 15 , wherein forming the interconnect layer stack comprises forming the plurality of patterned electrical conductor layers using thin film deposition.
21. The method of claim 15 , wherein the at least one circuit component comprises at least one integrated circuit.
22. The method of claim 15 , wherein the LCP solder mask has a thickness of less than 0.0015 inches.Cited by (0)
No later patents cite this yet.
References (0)
No backward citations on record.