Multi-role distributed line card

Abstract

A switch includes network ports and a network processor with a fabric interface that provides SerDes (Serializer/Deserializer) channels. The network processor divides each packet received over the network ports into cells and distributes the cells across the SerDes channels. Fabric ports of the switch communicate with the fabric interface to transmit cells to and receive cells from the fabric interface. The switch is selectively configurable as a standalone switch by connecting each fabric port of the switch to another of the fabric ports of the switch, as a member of a switch stack by connecting each fabric port of the switch to a different other switch through one fabric port of that other switch, or as a member of a distributed fabric system by connecting each fabric port of the switch to a different scaled-out fabric coupler (SFC) chassis by an SFC fabric port of that SFC chassis.

What is claimed is: 
     
       1. A network switch comprising:
 a plurality of network ports receiving packets over a network; 
 a network processor in communication with the network ports, the network processor having a fabric interface that provides a plurality of SerDes (Serializer/Deserializer) channels, the network processor dividing each packet received over the network ports into a plurality of cells and distributing the cells of each received packet across the SerDes channels; and 
 a plurality of fabric ports in communication with the fabric interface of the network processor to transmit cells to and receive cells from the fabric interface, each of the fabric ports being connected to one of the other fabric ports to produce a standalone network switch. 
 
     
     
       2. The network switch of  claim 1 , wherein each of the fabric ports includes a pluggable interface with a given number of lanes over which to transmit and receive cells, each lane of each pluggable interface being mapped to one of the SerDes channels of the fabric interfaces of the plurality of network processors. 
     
     
       3. The network switch of  claim 2 , wherein the pluggable interfaces are CXP interfaces. 
     
     
       4. The network switch of  claim 2 , wherein the given number of lanes is twelve. 
     
     
       5. The network switch of  claim 1 , wherein the network ports are selected from the group consisting of 10 Gigabit, 40 Gigabit, and 100 Gigabit Ethernet ports. 
     
     
       6. The network switch of  claim 1 , wherein each of the SerDes channels has a bandwidth in a range of approximately 10.3 Gbps to 11.5 Gbps. 
     
     
       7. The network switch of  claim 1 , wherein each of the SerDes channels has approximately a 25 Gbps bandwidth. 
     
     
       8. A switch stack comprising:
 a plurality of network switches, each network switch comprising:
 a plurality of network ports receiving packets over a network; 
 a network processor in communication with the network ports, the network processor having a fabric interface that provides a plurality of SerDes (Serializer/Deserializer) channels, the network processor dividing each packet received over the network ports into a plurality of cells and distributing the cells of each received packet across the SerDes channels; and 
 a plurality of fabric ports in communication with the fabric interface of the network processor to transmit cells to and receive cells from the fabric interface, each of the fabric ports including a pluggable interface with a given number of lanes over which to transmit and receive cells, each lane of each pluggable interface being mapped to one of the SerDes channels of the fabric interface of the network processor. 
 
 
     
     
       9. The switch stack of  claim 8 , wherein each pluggable interface is a CXP interface. 
     
     
       10. The switch stack of  claim 8 , wherein the given number of lanes is twelve. 
     
     
       11. The switch stack of  claim 8 , wherein the plurality of network ports of each network switch is selected from the group consisting of 10 Gigabit, 40 Gigabit, and 100 Gigabit Ethernet ports. 
     
     
       12. The switch stack of  claim 8 , wherein each of the SerDes channels has a bandwidth in a range of approximately 10.3 Gbps to 11.5 Gbps. 
     
     
       13. The switch stack of  claim 8 , wherein each of the SerDes channels has approximately a 25 Gbps bandwidth.