Array substrate for liquid crystal display having gate line, gate electrode and data pattern in at least two trenches and method of fabricating the same

Abstract

An array substrate includes: a trench having a depth from a surface of a substrate; a gate line, a gate electrode and a data pattern filling the respective trenches, wherein the data pattern is between the adjacent gate lines; a gate insulating layer on the gate line, the gate electrode and the data pattern, substantially flat over the substrate, and including contact holes that expose both ends of the data pattern, respectively; a data connection portion on the gate insulating layer and contacting the adjacent data patterns through the contact holes; a source electrode extending from the data connection portion, and a drain electrode spaced apart from the source electrode; a passivation layer on the source and drain electrodes and including a drain contact hole exposing the drain electrode; and a pixel electrode on the passivation layer and contacting the drain electrode through the drain contact hole.

What is claimed is: 
     
       1. An array substrate comprising:
 a substrate including a pixel region; 
 trenches formed in the substrate and having a depth from a surface of the substrate; 
 a gate line, a gate electrode and a data pattern filling at least two of the trenches, wherein the data pattern is between adjacent gate lines; 
 a gate insulating layer on the gate line, the gate electrode and the data pattern, substantially flat over the substrate, and including contact holes that expose ends of the data pattern; 
 a semiconductor layer on the gate insulating layer over the gate electrode; 
 a data connection portion on the gate insulating layer and contacting adjacent data patterns through the contact holes; 
 a source electrode connected to the data connection portion, and a drain electrode spaced apart from the source electrode; 
 a pixel electrode connected to the drain electrode; and 
 a passivation layer on the source and drain electrodes and including a drain contact hole exposing the drain electrode, 
 wherein the pixel electrode is on the passivation layer and contacts the drain electrode through the drain contact hole, and 
 wherein the source electrode extends from the data connection portion and on the semiconductor layer. 
 
     
     
       2. The array substrate according to  claim 1 , wherein the depth of the trenches is about 0.5 μm to about 5 μm, and the gate line, the gate electrode and the data pattern have a thickness equal to the depth. 
     
     
       3. An array substrate comprising:
 a substrate including a pixel region; 
 a buffer layer on the substrate and including trenches having a depth from a surface of the buffer layer; 
 a gate line, a gate electrode and a data pattern filling at least two of the trenches, wherein the data pattern is between adjacent gate lines; 
 a gate insulating layer over the buffer layer on the gate line, the gate electrode and the data pattern, substantially flat over the substrate, and including contact holes that expose both ends of the data pattern; 
 a semiconductor layer on the gate insulating layer over the gate electrode; 
 a data connection portion on the gate insulating layer and contacting adjacent data patterns through the contact holes; 
 a source electrode connected to the data connection portion, and a drain electrode spaced apart from the source electrode; and 
 a pixel electrode connected to the drain electrode. 
 
     
     
       4. The array substrate according to  claim 3 , further comprising:
 a passivation layer on the source and drain electrodes and including a drain contact hole exposing the drain electrode, 
 wherein the pixel electrode is on the passivation layer and contacts the drain electrode through the drain contact hole, and 
 wherein the source electrode extends from the data connection portion and on the semiconductor layer. 
 
     
     
       5. The array substrate according to  claim 3 , wherein the depth of the trenches is 0.5 μm to 5 μm, and the gate line, the gate electrode and the data pattern have a thickness that is the same as the depth. 
     
     
       6. The array substrate according to  claim 3 , wherein the depth of the trenches is equal to or less than a thickness of the buffer layer. 
     
     
       7. A method of fabricating an array substrate comprising:
 etching a substrate including a pixel region to form trenches in the substrate and having a depth from a surface of the substrate; 
 forming a gate line, a gate electrode and a data pattern filling at least two of the trenches, wherein the data pattern is between adjacent gate lines; 
 forming a gate insulating layer on the gate line, the gate electrode and the data pattern, the gate insulating layer being substantially flat over the substrate; 
 forming a semiconductor layer on the gate insulating layer over the gate electrode; 
 patterning the gate insulating layer to form contact holes that expose ends of the data pattern; 
 forming a data connection portion on the gate insulating layer, the data connection portion contacting adjacent data patterns through the contact holes, a source electrode connected to the data connection portion, and a drain electrode spaced apart from the source electrode; 
 after forming the data connection portion on the gate insulating layer, forming a passivation layer on the source and drain electrodes, the passivation layer including a drain contact hole exposing the drain electrode; and 
 forming a pixel electrode connected to the drain electrode, 
 wherein the pixel electrode is on the passivation layer and contacts the drain electrode through the drain contact hole, and 
 wherein the source electrode extends from the data connection portion and on the semiconductor layer. 
 
     
     
       8. The method according to  claim 7 , wherein etching the substrate including the pixel region to form the trenches in the substrate and having the depth from a surface of the substrate, and forming the gate line, the gate electrode and the data pattern filling the at least two trenches comprises:
 forming a photoresist pattern on the substrate and exposing a portion corresponding to the trenches; 
 etching the substrate using the photoresist pattern to form the trenches; 
 forming a catalytic layer on the trenches and the photoresist pattern; 
 removing the photoresist pattern, whereby the catalytic layer remains in the trenches; and 
 immersing the substrate having the catalytic layer remaining in the trenches into a plating solution in which a metal material is dissolved and performing an electroless plating, thereby plating the metal material in the trenches. 
 
     
     
       9. The method according to  claim 7 , wherein the depth of the trenches is 0.5 μm to 5 μm. 
     
     
       10. The method according to  claim 8 , wherein the catalytic layer is formed by coating Pd-Sn colloid or depositing Pd ion. 
     
     
       11. A method of fabricating an array substrate comprising:
 forming a buffer layer on a substrate including a pixel region; 
 etching the buffer layer to form trenches in the buffer layer and having a depth from a surface of the buffer layer; 
 forming a gate line, a gate electrode and a data pattern filling at least two of the trenches, wherein the data pattern is between adjacent gate lines; 
 forming a gate insulating layer over the buffer layer on the gate line, the gate electrode and the data pattern, and substantially flat over the substrate; 
 forming a semiconductor layer on the gate insulating layer over the gate electrode; 
 patterning the gate insulating layer to form contact holes that expose ends of the data pattern; 
 forming a data connection portion on the gate insulating layer, which contacts adjacent data patterns through the contact holes, a source electrode connected to the data connection portion, and a drain electrode spaced apart from the source electrode; and 
 forming a pixel electrode connected to the drain electrode. 
 
     
     
       12. The method according to  claim 11 , further comprising:
 after forming the data connection portion on the gate insulating layer, forming a passivation layer on the source and drain electrodes, the passivation layer including a drain contact hole exposing the drain electrode, 
 wherein the pixel electrode is on the passivation layer and contacts the drain electrode through the drain contact hole, and 
 wherein the source electrode extends from the data connection portion and on the semiconductor layer. 
 
     
     
       13. The method according to  claim 11 , wherein etching the buffer layer to form the trenches in the buffer layer and having the depth from a surface of the buffer layer, and forming the gate line, the gate electrode and the data pattern filling the at least two trenches comprises:
 forming a photoresist pattern on the buffer layer which exposes a portion corresponding to the trenches; 
 etching the buffer layer using the photoresist pattern to form the trenches; 
 forming a catalytic layer on the trenches and the photoresist pattern; 
 removing the photoresist pattern, whereby the catalytic layer remains in the trenches; and 
 immersing the substrate having the catalytic layer remaining in the trenches into a plating solution in which a metal material is dissolved and performing an electroless plating, thereby plating the metal material in the trenches. 
 
     
     
       14. The method according to  claim 13 , wherein the catalytic layer is formed by coating Pd-Sn colloid or depositing Pd ion. 
     
     
       15. The method according to  claim 11 , wherein the depth of the trenches is equal to or less than a thickness of the buffer layer. 
     
     
       16. The method according to  claim 11 , wherein the depth of the trenches is 0.5 μm to 5 μm.