Display device with improved driver for array of cells capable of storing charges

Abstract

Provided is a display device including a driver circuit for controlling supply of charges to an array of cells capable of storing the charges. In the driver circuit, a preceding electrically connecting part (SW 221 ) controlled by a clock signal (CLK 1 ) electrically connects an output signal line of a first circuit ( 211 ) having a positive polarity which is a potential higher than a reference potential and an output signal line of a second circuit ( 212 ) having a negative polarity which is a potential lower than the reference potential. After a predetermined time period has elapsed, a subsequent electrically connecting part (SW 222 ) controlled by a clock signal (CLK 2 ) electrically connects an output signal line of a third circuit ( 213 ) having the positive polarity and an output signal line of a fourth circuit ( 214 ) having the negative polarity.

What is claimed is: 
     
       1. A display device, comprising:
 an array of cells capable of storing charges; and 
 a driver circuit which controls supply of the charges to the array of the cells, the driver circuit comprising: 
 a first circuit, a second circuit, a third circuit, and a fourth circuit, which are connected to a first output signal line, a second output signal line, a third output signal line, and a fourth output signal line, respectively, and supply the charges to a plurality of different cells in the array, the first output signal line, the second output signal line, the third output signal line, and the fourth output signal line being sequentially adjacent to one another in this order; 
 a first preceding electrically connecting means which electrically connects the second output signal line having a potential different from a potential of the first output signal line and the first output signal line to each other; and 
 a first subsequent electrically connecting means which electrically connects, at a timing after an electrical connection has been made by the first preceding electrically connecting means, the third output signal line having a potential different from a potential of the fourth output signal line and the fourth output signal line to each other, 
 wherein the first output signal line, the second output signal line, the third output signal line, and the fourth output signal line are each applied with one of a voltage having a positive polarity which is a potential higher than a reference potential or a voltage having a negative polarity which is a potential lower than the reference potential, 
 wherein the third output signal line is applied with a voltage having the same polarity as a polarity of the first output signal line, and 
 wherein the second output signal line and the fourth output signal line are each applied with a voltage having a polarity different from the polarity of the first output signal line, and 
 the first preceding electrically connecting means is configured to be controlled by a first clock signal which has a cycle of one horizontal synchronization period, 
 the first subsequent electrically connecting means is configured to be controlled by a second clock signal which has a cycle of one horizontal synchronization period, and 
 the second clock signal has a different phase from that of the first clock signal. 
 
     
     
       2. The display device according to  claim 1 , wherein the driver circuit further comprises:
 a preceding clock signal generating means which generates the first clock signal controlling a timing of the electrical connection made by the preceding electrically connecting means; and 
 a subsequent clock signal generating means which generates the second clock signal controlling a timing of the electrical connection made by the subsequent electrically connecting means. 
 
     
     
       3. A display device, comprising:
 an array of cells capable of storing charges; 
 a driver circuit which controls supply of the charges to the array of the cells, 
 the driver circuit comprising a first circuit, a second circuit, a third circuit, and a fourth circuit which outputs output signals supplying the charges to a plurality of different cells in the array, 
 wherein the output signals are each one of a voltage having a positive polarity which is a potential higher than a reference potential or a voltage having a negative polarity which is a potential lower than the reference potential, 
 wherein the first circuit includes a first output signal line to which one of the output signals is applied, 
 wherein the second circuit includes a second output signal line to which another one of the output signals is applied, which has a polarity different from a polarity of the one of the output signals applied to the first output signal line, wherein the third circuit includes a third output signal line to which still another one of the output signals is applied, which has the same polarity as the polarity of the one of the output signals applied to the first output signal line, 
 wherein the fourth circuit includes a fourth output signal line to which a further one of the output signals is applied, which has a polarity different from the polarity of the one of the output signals applied to the first output signal line, 
 wherein the driver circuit further comprises: 
 a preceding electrically connecting means which electrically connects a potential of the first output signal line and a potential of the second output signal line to each other; and 
 a subsequent electrically connecting means which electrically connects, at a timing after an electrical connection has been made by the preceding electrically connecting means, a potential of the third output signal line and a potential of the fourth output signal line to each other, and 
 wherein the first output signal line, the second output signal line, the third output signal line, and the fourth output signal line are sequentially adjacent to one another in this order, 
 the preceding electrically connecting means is configured to be controlled by a first clock signal which has a cycle of one horizontal synchronization period, 
 the subsequent electrically connecting means is configured to be controlled by a second clock signal which has a cycle of one horizontal synchronization period, and 
 the second clock signal has a different phase from that of the first clock signal. 
 
     
     
       4. The display device according to  claim 3 , wherein the driver circuit further comprises:
 a preceding clock signal generating means which generates the first clock signal controlling a timing of the electrical connection made by the preceding electrically connecting means; and 
 a subsequent clock signal generating means which generates the second clock signal controlling a timing of the electrical connection made by the subsequent electrically connecting means, the clock signal having a same cycle and a different phase from a cycle and a phase of the clock signal generated by the preceding clock signal generating means.