P
US9070602B2ActiveUtilityPatentIndex 51

Method for fabricating liquid crystal display

Assignee: YE XIN TECHNOLOGY CONSULTING CO LTDPriority: Jun 6, 2013Filed: Jun 5, 2014Granted: Jun 30, 2015
Est. expiryJun 6, 2033(~6.9 yrs left)· nominal 20-yr term from priority
Inventors:KAO YI-CHUN
H10D 64/01354H10D 86/443H10D 86/0231H10D 86/60H10D 86/021G02F 1/13452H01L 27/1259H01L 21/28247G02F 1/136227
51
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References
11
Claims

Abstract

Method for manufacturing a thin film transistor liquid crystal display is provided. A substrate is provided. A gate electrode, a source electrode, a drain electrode, and a passivation film are formed on the substrate in sequence. The passivation film has a contact hole to expose a part of the drain electrode. A conductive layer is formed by coating nano metal material on the passivation film and in the contract hole from which the drain electrode is exposed. A pixel electrode is formed by patterning the conductive layer.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A method for fabricating a thin film transistor (TFT) liquid crystal display, the method comprising:
 providing a substrate; 
 forming a gate electrode, a source electrode, a drain electrode, and a passivation film on the substrate in sequence, the passivation film having a contact hole to expose a part of the drain electrode; 
 forming a conductive layer by coating nano metal material on the passivation film and the part of the drain electrode exposed from the contract hole; 
 forming a pixel electrode by patterning the conductive layer; and 
 plating the pixel electrode for flatting a surface of the pixel electrode. 
 
     
     
       2. The method of  claim 1 , wherein the nano metal materiel is nano particles or nano wires. 
     
     
       3. The method of  claim 2 , wherein the nano metal materiel is made of silver or copper. 
     
     
       4. The method of  claim 2 , wherein the nano particles or nano wires each have a dimension between  1  nanometer to 50 nanometers. 
     
     
       5. The method of  claim 1 , wherein the gate electrode, the source electrode, the drain electrode, and the passivation film on the substrate are performed via independent photo-mask processes, respectively. 
     
     
       6. The method of  claim 1 , wherein the step of forming a pixel electrode is performed by a photo-mask process, in which a fifth mask and a fifth photo-resist layer are provided for covering the conductive layer. 
     
     
       7. The method of  claim 6 , wherein a predetermined pattern according to the fifth mask is formed on the fifth photo-resist layer after an exposure and development process. 
     
     
       8. The method of  claim 7 , wherein the pixel electrode is formed by etching the conductive layer according to the predetermined pattern. 
     
     
       9. The method of  claim 1 , wherein a plurality of supplementary steps are performed after the step of plating the pixel electrode for flatting a surface of the pixel electrode, the supplementary steps comprising:
 forming a covering film on the pixel electrode; and 
 baking the pixel electrode. 
 
     
     
       10. The method of  claim 9 , wherein the covering film is an organic film coated on both of the pixel electrode and the passivation film. 
     
     
       11. The method of  claim 9 , wherein the step of baking the pixel electrode is lasted for at least one hour and under a temperature of at least 180 degrees Celsius.

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