Semiconductor structure and manufacturing process thereof

Abstract

A semiconductor structure includes a substrate having a first conductive type, a well having a second conductive type formed in the substrate, a first doped region and a second doped region formed in the well, a field oxide, a first dielectric layer and a second dielectric layer. The field oxide is formed on a surface region of the well and between the first doped region and the second doped region. The first dielectric layer is formed on the surface region of the well and covers an edge portion of the field oxide. The first dielectric layer has a first thickness. The second dielectric layer is formed on the surface region of the well. The second dielectric layer has a second thickness smaller than the first thickness.

What is claimed is: 
     
       1. A manufacturing process of a semiconductor, the process comprising:
 providing a substrate having a first conductive type; 
 forming a well having a second conductive type in the substrate; 
 forming a first doped region and a second doped region in the well; 
 forming a field oxide on a surface region of the well and between the first doped region and the second doped region; 
 forming a first dielectric layer on the surface region of the well and covering an edge portion of the field oxide, wherein the first dielectric layer has a first thickness; 
 forming a second dielectric layer on the surface region of the well, wherein the second dielectric layer has a second thickness smaller than the first thickness; and 
 forming a gate conductive layer on a portion of the field oxide covered by the first dielectric layer, wherein the size of an area of the field oxide covered by the first dielectric layer is greater than the size of an area of the field oxide covered by the gate conductive layer. 
 
     
     
       2. The process according to  claim 1 , wherein the first dielectric layer and the second dielectric layer are not overlapped. 
     
     
       3. The process according to  claim 1 , wherein the first dielectric layer is a first gate oxide layer, the second dielectric layer is a second gate oxide layer. 
     
     
       4. The process according to  claim 1 , wherein a channel region is formed between the field oxide and the second doped region, the first dielectric layer covers a part of the channel region and a part of the field oxide. 
     
     
       5. The process according to  claim 1 , wherein a channel region is formed between the field oxide and the second doped region, the first dielectric layer covers a part of the channel region and a part of the second doped region. 
     
     
       6. The process according to  claim 1 , wherein the first doped region is a drain doped region, the second doped region is a source doped region, the field oxide is connected to the first doped region, and a gap is formed between the field oxide and the second doped region. 
     
     
       7. The process according to  claim 1 , wherein the gate conductive layer is formed on the first dielectric layer and the second dielectric layer. 
     
     
       8. The process according to  claim 7 , wherein an end portion of the first dielectric layer is exposed from the gate conductive layer. 
     
     
       9. The process according to  claim 1 , wherein a portion of the first dielectric layer is covered by a mask layer and an etching process is conducted to define a pattern of the first dielectric layer.