Frequency shift-keying reader circuit

Abstract

A frequency shift-keying reader circuit includes a band-pass filter, a low noise amplifier, a first balun, an injection-lock divide-by-2 frequency divider, a sub-harmonic mixer and a low-pass filter. The band-pass filter performs a filtering procedure to a radio frequency signal, wherein the filtered radio-frequency signal is received by the low noise amplifier to provide an injection signal, and the injection signal is received by the first balun to generate a first differential signal and a second differential signal. The injection signal is received by the injection-lock divide-by-2 frequency divider to provide a first oscillation signal and a second oscillation signal, wherein the first differential signal, the second differential signal, the first oscillation signal and the second oscillation signal are received by the sub-harmonic mixer for performing a mixing procedure and thereafter generating an output signal, the low-pass filter performs a filtering procedure to the output signal.

What is claimed is: 
     
       1. A frequency shift-keying reader circuit includes:
 a band-pass filter for receiving a radio frequency signal and performing a filtering procedure, wherein the radio frequency signal comprises an operational frequency; 
 a low noise amplifier for connecting to the band-pass filter and receiving the filtered radio frequency signal, wherein the low noise amplifier is used for amplifying the radio frequency signal to provide an injection signal; 
 a first balun for connecting to the low noise amplifier and receiving the injection signal, the first balun generates the first differential signal and the second differential signal, wherein the first differential signal and the second differential signal are mutually inverted; 
 an injection-lock divide-by-2 frequency divider for connecting to the low noise amplifier and receiving the injection signal, wherein the injection-lock divide-by-2 frequency divider is locked at a lock frequency by the injection signal, the lock frequency is half the operational frequency, the injection-lock divide-by-2 frequency divider provides a first oscillation signal and a second oscillation signal, wherein the first oscillation signal and the second oscillation signal are mutually inverted; 
 a sub-harmonic mixer for connecting to the first balun and the injection-lock divide-by-2 frequency divider, the sub-harmonic mixer receives the first differential signal, the second differential signal, the first oscillation signal and the second oscillation signal for performing a mixing procedure and generates an output signal; and 
 a low-pass filter, the low-pass filter connects to the sub-harmonic mixer and performs a filtering procedure to the output signal. 
 
     
     
       2. The frequency shift-keying reader circuit in accordance with  claim 1 , wherein the low noise amplifier comprises an inductor, a first capacitor, a first N-type transistor and a second N-type transistor, one end of the inductor receives the filtered radio frequency signal, the other end of the inductor connects to one end of the first capacitor, the other end of the first capacitor connects to a gate terminal of the first N-type transistor, the gate terminal of the first N-type transistor receives a first bias voltage, a source terminal of the first N-type transistor is grounded, a source terminal of the second N-type transistor connects to a drain terminal of the first N-type transistor, wherein a gate terminal of the second N-type transistor and a drain terminal of the second N-type transistor connects to a first power terminal. 
     
     
       3. The frequency shift-keying reader circuit in accordance with  claim 2 , wherein the low noise amplifier comprises a first bias resistor and a first resistor, the gate terminal of the first N-type transistor receives the first bias voltage via the first bias resistor, the drain terminal of the second N-type transistor connects to the first power terminal via the first transistor. 
     
     
       4. The frequency shift-keying reader circuit in accordance with  claim 2 , wherein the first balun comprises a second capacitor, a third N-type transistor and a fourth N-type transistor, one end of the second capacitor connects to the drain terminal of the second N-type transistor, the other end of the second capacitor connects to a gate terminal of the third N-type transistor, the gate terminal of the third N-type transistor receives a second bias voltage, a drain terminal of the third N-type transistor connects to the first power terminal, a drain terminal of the fourth N-type transistor connects to a source terminal of the third N-type transistor, wherein a gate terminal of the fourth N-type transistor and a source terminal of the fourth N-type transistor are grounded, wherein the drain terminal of the third N-type transistor and the source terminal of the third N-type transistor provide the first differential signal and the second differential signal respectively. 
     
     
       5. The frequency shift-keying reader circuit in accordance with  claim 4 , wherein the first balun comprises a second bias resistor, a second resistor and a third resistor, the gate terminal of the third N-type transistor receives the second bias voltage via the second bias resistor, the drain terminal of the third N-type transistor connects to the first power terminal via the second resistor, and the source terminal of the third N-type transistor is grounded via the third resistor. 
     
     
       6. The frequency shift-keying reader circuit in accordance with  claim 4 , wherein the injection-lock divide-by-2 frequency divider comprises a ring oscillator and a second balun, the ring oscillator connects to the low noise amplifier, the second balun connects to the ring oscillator, and the second balun outputs the first oscillation signal and the second oscillation signal. 
     
     
       7. The frequency shift-keying reader circuit in accordance with  claim 6 , wherein the ring oscillator comprises a first oscillation device, a plurality of second oscillation devices, a current source, an input transistor and a third capacitor, the first oscillation device comprises a first P-type oscillating transistor and a first N-type oscillating transistor, each of the second oscillation devices comprises a second P-type oscillating transistor and a second N-type oscillating transistor, wherein a gate terminal of the first P-type oscillating transistor receives a third bias voltage, a source terminal of the first P-type oscillating transistor connects to a second power terminal, a body terminal of the first P-type oscillating transistor receives an adjusting voltage, a drain terminal of the first N-type oscillating transistor connects to a drain terminal of the first P-type oscillating transistor, a gate terminal of the first N-type oscillating transistor connects to a drain terminal of the input transistor and a drain terminal of one of the second N-type oscillating transistors, wherein a source terminal of the first N-type oscillating transistor connects to the current source, a gate terminal of each of the second P-type oscillating transistors receives the third bias voltage, a source terminal of each of the second P-type oscillating transistors connects to the second power terminal, a body terminal of each of the second P-type oscillating transistors receives the adjusting voltage, a drain terminal of each of the second N-type oscillating transistors connects to a drain terminal of the second P-type oscillating transistor, a gate terminal of each of the second N-type oscillating transistors connects to the drain terminal of another second N-type oscillating transistor, the gate terminal of one of the second N-type oscillating transistors connects to the drain terminal of the first N-type oscillating transistor, a source terminal of each of the second N-type oscillating transistors connects to the current source, a gate terminal of the input transistor receives a fourth bias voltage and connects to the drain terminal of the second N-type oscillating transistor via the third capacitor for receiving the injection signal, and a source terminal of the input transistor connects to the drain terminal of the first N-type oscillating transistor. 
     
     
       8. The frequency shift-keying reader circuit in accordance with  claim 7 , wherein the ring oscillator comprises a first input resistor, a plurality of second input resistors, a third bias resistor and a fourth bias resistor, the body terminal of the first P-type oscillating transistor receives the adjusting voltage via the first input resistor, the gate terminal of the first P-type oscillating transistor receives the third bias voltage via the third bias resistor, the body terminal of each of the second P-type oscillating transistors receives the adjusting voltage via each of the second input resistors, the gate terminal of each of the second P-type oscillating transistors receives the third bias voltage via the third bias resistor, and the gate terminal of the input transistor receives the fourth bias voltage via the fourth bias resistor. 
     
     
       9. The frequency shift-keying reader circuit in accordance with  claim 7 , wherein the second balun comprises a fourth capacitor, a fifth N-type transistor and a sixth N-type transistor, one end of the fourth capacitor connects to the drain terminal of the first N-type oscillating transistor, the other end of the fourth capacitor connects to a gate terminal of the fifth N-type transistor, the gate terminal of the fifth N-type transistor receives a fifth bias voltage, a drain terminal of the fifth N-type transistor connects to the first power terminal, a drain terminal of the sixth N-type transistor connects to a source terminal of the fifth N-type transistor, wherein a gate terminal of the sixth N-type transistor and a source terminal of the sixth N-type transistor are grounded, wherein the drain terminal of the fifth N-type transistor and the source terminal of the fifth N-type transistor provide the first oscillation signal and the second oscillation signal respectively. 
     
     
       10. The frequency shift-keying reader circuit in accordance with  claim 9 , wherein the second balun comprises a fifth bias resistor, a fourth resistor and a fifth resistor, the gate terminal of the fifth N-type transistor receives the fifth bias voltage via the fifth bias resistor, the drain terminal of the fifth N-type transistor connects to the first power terminal via the fourth resistor, and the source terminal of the fifth N-type transistor is grounded via the fifth resistor. 
     
     
       11. The frequency shift-keying reader circuit in accordance with  claim 1 , wherein the sub-harmonic mixer comprises a transconductance stage and a switch stage connected to the transconductance stage, the transconductance stage receives the first differential signal and the second differential signal and outputs the output signal, and the switch stage receives the first oscillation signal and the second oscillation signal. 
     
     
       12. The frequency shift-keying reader circuit in accordance with  claim 11 , wherein the transconductance stage comprises a first differential transistor and a second differential transistor, a gate terminal of the first differential transistor receives the first differential signal and a sixth bias voltage, a drain terminal of the first differential transistor connects to the first power terminal, a gate terminal of the second differential transistor receives the second differential signal and a seventh bias voltage, a drain terminal of the second differential transistor connects to the first power terminal, wherein the voltage difference between the drain terminal of the first differential transistor and the drain terminal of the second differential transistor is the output signal. 
     
     
       13. The frequency shift-keying reader circuit in accordance with  claim 12 , wherein the sub-harmonic mixer comprises a first coupling capacitor, second coupling capacitor, a sixth bias resistor, a sixth resistor, a seventh bias resistor and a seventh resistor, the gate terminal of the first differential transistor receives the first differential signal via the first coupling capacitor, the gate terminal of the first differential transistor receives the sixth bias voltage via the sixth bias resistor, the drain terminal of the first differential transistor connects to the first power terminal via the sixth resistor, the gate terminal of the second differential transistor receives the second differential signal via the second coupling capacitor, the gate terminal of the second differential transistor receives the seventh bias voltage via the seventh bias resistor, the drain terminal of the second differential transistor connects to the first power terminal via the seventh resistor. 
     
     
       14. The frequency shift-keying reader circuit in accordance with  claim 12 , wherein the switch stage comprises a third differential transistor and a fourth differential transistor, a gate terminal of the third differential transistor receives the first oscillation signal and an eighth bias voltage, a gate terminal of the fourth differential transistor receives the second oscillation signal and a ninth bias voltage, wherein a drain terminal of the third differential transistor and a drain terminal of the fourth differential transistor connect to a source terminal of the first differential transistor and a source terminal of the second differential transistor, wherein a source terminal of the third differential transistor and a source terminal of the fourth differential transistor are grounded. 
     
     
       15. The frequency shift-keying reader circuit in accordance with  claim 14 , wherein the sub-harmonic mixer comprises a third coupling capacitor, a fourth coupling capacitor, an eighth bias resistor and a ninth bias resistor, the gate terminal of the third differential transistor receives the first oscillation signal via the third coupling capacitor, the gate terminal of the third differential transistor receives the eighth bias voltage via the eighth bias resistor, the gate terminal of the fourth differential transistor receives the second oscillation signal via the fourth coupling capacitor, and the gate terminal of the fourth differential transistor receives the ninth bias voltage via the ninth bias resistor.