Semiconductor memory apparatus and method of operating using the same

Abstract

A semiconductor memory apparatus includes a resistive memory cell coupled between a bit line and a bit line bar; a control unit configured to couple the bit line to a first node and apply a reference voltage to a second node in response to a first sense amplifier enable signal and a second sense amplifier enable signal; a data output sense amplifier configured to sense and amplify a voltage of the first node and a voltage of the second node; a data transfer unit configured to couple the first and second nodes to a data line and a data line bar in response to a column select signal; and a data input unit configured to drive the bit line and the bit line bar according to voltage levels of the first and second nodes in response to a write enable signal.

What is claimed is: 
     
       1. A semiconductor memory apparatus comprising:
 a resistive memory cell coupled between a bit line and a bit line bar; 
 a control unit configured to couple the bit line to a first node in response to a first sense amplifier enable signal and a second sense amplifier enable signal, and apply a reference voltage to a second node in response to the second sense amplifier enable signal; 
 a data output sense amplifier configured to sense and amplify a voltage of the first node and a voltage of the second node; 
 a data transfer unit configured to couple the first and second nodes to a data line and a data line bar in response to a column select signal; and 
 a data input unit configured to drive the bit line and the bit line bar according to voltage levels of the first and second nodes in response to a write enable signal. 
 
     
     
       2. The semiconductor memory apparatus according to  claim 1 , wherein the second sense amplifier enable signal is acquired by delaying the first sense amplifier enable signal. 
     
     
       3. The semiconductor memory apparatus according to  claim 2 , wherein the control unit applies a specified voltage level to the bit line and couples the bit line bar to a ground terminal when the first sense amplifier enable signal is enabled, and couples the first and second nodes to the data output sense amplifier when the second sense amplifier enable signal is enabled. 
     
     
       4. The semiconductor memory apparatus according to  claim 1 , wherein the data transfer unit couples the first node to the data line and couples the second node to the data line bar when the column select signal is enabled. 
     
     
       5. The semiconductor memory apparatus according to  claim 1 , wherein the data input unit lowers a voltage level of the bit line and raises a voltage level of the bit line bar when the voltage level of the first node is higher than the voltage level of the second node in the case where the write enable signal is enabled, and raises a voltage level of the bit line and lowers a voltage level of the bit line bar when the voltage level of the first node is lower than the voltage level of the second node in the case where the write enable signal is enabled. 
     
     
       6. The semiconductor memory apparatus according to  claim 1 , further comprising:
 a first dummy resistive memory cell having a data value of a low level; 
 a second dummy resistive memory cell having a data value of a high level; and 
 a reference voltage generation unit coupled to the first and second dummy resistive memory cells and configured to generate the reference voltage which has a voltage level corresponding to an average value of the data value of the low level and the data value of the high level. 
 
     
     
       7. A semiconductor memory apparatus comprising:
 a control unit configured to couple a bit line to a data output sense amplifier in a read operation; 
 the data output sense amplifier configured to sense and amplify a voltage level of the bit line when the data output sense amplifier is coupled to the bit line; 
 a data transfer unit configured to receive a column select signal and couple a data line to the data output sense amplifier and to a data input unit in response to the column select signal in a read or write operation; and 
 the data input unit comprising a transfer transistor configured to transfer data from the data transfer unit onto the bit line by transferring a voltage level corresponding to a voltage level of the data line to the bit line in response to the voltage level on the data line. 
 
     
     
       8. The semiconductor memory apparatus according to  claim 7 , wherein the control unit couples the bit line to the data output sense amplifier when a sense amplifier enable signal is enabled and decouples the bit line and the data output sense amplifier when the sense amplifier enable signal is disabled. 
     
     
       9. The semiconductor memory apparatus according to  claim 7 , wherein the data transfer unit couples the data line to the data output sense amplifier and the data input unit when a column select signal is enabled. 
     
     
       10. A semiconductor memory apparatus comprising:
 a resistive memory cell coupled between a bit line and a bit line bar; 
 a control unit configured to couple the bit line to a data output sense amplifier and couple the bit line bar to a ground terminal in response to a sense amplifier enable signal; 
 the data output sense amplifier configured to compare a voltage level of the bit line with a level of a reference voltage and amplify a difference thereof, when the data output sense amplifier is coupled to the bit line; 
 a data input unit configured to generate voltage levels of the bit line and the bit line bar according to voltage levels of a data line and a data line bar in response to a write enable signal, when the data input unit is coupled to the data line and the data line bar; and 
 a data transfer unit configured to couple or decouple the data line to and from the data output sense amplifier and the data input unit in response to a column select signal. 
 
     
     
       11. The semiconductor memory apparatus according to  claim 10 , wherein the control unit couples the bit line to the data output sense amplifier and couples the bit line bar to the ground terminal when the sense amplifier enable signal is enabled, and decouples the bit line from the data output sense amplifier and decouples the bit line bar from the ground terminal when the sense amplifier enable signal is disabled. 
     
     
       12. The semiconductor memory apparatus according to  claim 10 , wherein the data input unit raises the voltage level of any one of the bit line and the bit line bar and lowers the voltage level of the other of the bit line and the bit line bar, in response to the voltage levels of the data line and the data line bar. 
     
     
       13. The semiconductor memory apparatus according to  claim 10 , wherein the reference voltage has a voltage level corresponding to an average value when the resistive memory cell has data of a high level and a low level. 
     
     
       14. A method of operating a semiconductor memory apparatus, comprising:
 coupling a resistive memory cell between a bit line and a bit line bar; 
 coupling the bit line to a first node in response to a first sense amplifier enable signal and a second sense amplifier enable signal, and applying a reference voltage to a second node in response to the second sense amplifier enable signal; 
 sensing and amplifying a voltage of the first node and a voltage of the second node; 
 coupling the first and second nodes to a data line and a data line bar in response to a column select signal; and 
 driving the bit line and the bit line bar according to voltage level of the first and second nodes in response to a write enable signal. 
 
     
     
       15. The method of  claim 14 , wherein the second sense amplifier enable signal is acquired by delaying the first sense amplifier enable signal. 
     
     
       16. The method of  claim 15 , further comprising:
 applying a specified voltage level to the bit line and coupling the bit line bar to a ground terminal when the first sense amplifier enable signal is enabled; and 
 coupling the first and second nodes to the data output sense amplifier when the second sense amplifier enable signal is enabled. 
 
     
     
       17. The method of  claim 14 , further comprising:
 coupling the first node to the data line and coupling the second node to the data line bar when the column select signal is enabled. 
 
     
     
       18. The method of  claim 14 , further comprising:
 lowering a voltage level of the bit line and raising a voltage level of the bit line bar when the voltage level of the first node is higher than the voltage level of the second node in the case where the write enable signal is enabled; and 
 raising a voltage level of the bit line and lowering a voltage level of the bit line bar when the voltage level of the first node is lower than the voltage level of the second node in the case where the write enable signal is enabled. 
 
     
     
       19. The method of  claim 14 , further comprising:
 providing a first dummy resistive memory cell having a data value of a low level; 
 providing a second dummy resistive memory cell having a data value of a high level; and 
 coupling to the first and second dummy resistive memory cells through a reference voltage generation unit and generating the reference voltage which has a voltage level corresponding to an average value of the data value of the low level and the data value of the high level.