US9105611B2ActiveUtilityPatentIndex 38
Power module package
Est. expiryOct 31, 2031(~5.3 yrs left)· nominal 20-yr term from priority
H10W 90/756H10W 90/753H10W 74/00H10W 90/811H10W 70/468H10W 70/442H10W 90/00H10W 70/40H10W 40/00H10W 40/778H10W 70/692H01L 23/49575H01L 23/4334H01L 2924/1305H01L 2924/13055H01L 2924/00014H01L 2224/48247H01L 2224/48137H01L 23/49537H01L 2924/00H01L 2924/13091H01L 23/49531H01L 2924/13034
38
PatentIndex Score
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Cited by
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References
6
Claims
Abstract
Disclosed herein is a power module package including: a substrate having a ceramic layer formed in one surface thereof; a circuit pattern formed on the ceramic layer; a first lead frame having one side contacting the circuit pattern and the other side protruding toward the outside; and a first semiconductor chip mounted on one side of the first lead frame.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1. A power module package, comprising:
a substrate having a ceramic layer having thickness from 1 micron to 500 microns and formed in one surface thereof;
a circuit pattern formed on the ceramic layer;
a first lead frame having one side contacting the circuit pattern and the other side protruding toward the outside;
a first semiconductor chip which is a power device and mounted on one side of the first lead frame;
a second lead frame spaced apart from the first lead frame and electrically connected to the first semiconductor chip; and
a second semiconductor chip which is a control device and mounted on the second lead frame,
wherein the substrate is one selected from the group consisting of a metal substrate, a printed circuit board, an insulated metal substrate and a pre-molded substrate and combinations thereof, and
wherein the substrate and the circuit pattern are formed only under the first lead frame, and the ceramic layer is not sintered using a direct bonded copper substrate.
2. The power module package as set forth in claim 1 , further comprising:
a bonding layer formed between the circuit pattern and the first lead frame.
3. The power module package as set forth in claim 1 , wherein the circuit pattern includes an electroless plating layer and an electroplating layer.
4. The power module package as set forth in claim 1 , wherein the first lead frame and the second lead frame are formed to have a step therebetween.
5. The power module package as set forth in claim 1 , further comprising:
a molding material formed to surround the first semiconductor chip from a side of the substrate.
6. The power module package as set forth in claim 1 , wherein the substrate is a metal substrate.Cited by (0)
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