ADC testing

Abstract

A histogram-based method for testing an electronic converter device, such as an analogue to digital converter, includes steps of defining at least one histogram hyperbin arranged to store hits for at least one subrange of output codes; applying an input test stimulus to an input of the device to test a subrange of output codes matched to the hyperbin; and accumulating the histogram. At least two hyperbins may be provided, each bin being arranged to store hits for at least one subrange of output codes, and the input test stimulus is applied to an input of the device to test a subrange of output codes matched to one of the hyperbins. Both hyperbins may be open while the histogram is being accumulated for any subrange of output codes. The method may further involve varying the input stimulus to test another subrange.

The invention claimed is: 
     
       1. A method for sequentially incrementing a test stimulus voltage using a feedback circuit that has an inverting input, an output and a feedback capacitor connected between the inverting input and the output, the method comprising successively sampling an output voltage; applying the output voltage to the feedback capacitor to create a DC level change between the inverting input and output terminals on the feedback circuit; and applying the DC level change to the test stimulus voltage. 
     
     
       2. A method as claimed in  claim 1  wherein the feedback circuit is an op amp. 
     
     
       3. A method as claimed in  claim 1  wherein a ramp is used to control an amount by which the output voltage is to be incremented. 
     
     
       4. A method as claimed in  claim 3  wherein a DAC is used to control the amount by which the output voltage is incremented. 
     
     
       5. A circuit for applying a DC offset level to an input signal, the circuit comprising:
 a unity gain buffer that has an inverting input, a non-inverting input and an output; 
 a feedback capacitor connected between the inverting input and the output; and 
 a sampling capacitor connected between the output of the unity gain buffer and earth, so that it can be charged, 
 wherein:
 the feedback capacitor defines a DC offset level. 
 
 
     
     
       6. A circuit as claimed in  claim 5  wherein the unity gain buffer is a unity gain operational amplifier. 
     
     
       7. A circuit as claimed in  claim 5  comprising one or more switches for switching the feedback capacitor and the sampling capacitor, so that the charged sampling capacitor defines the DC offset level.