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US9110342B2ActiveUtilityPatentIndex 38

TFT array substrate, liquid crystal panel having the same, and method of manufacturing the TFT array substrate

Assignee: MITSUBISHI ELECTRIC CORPPriority: Nov 12, 2012Filed: Oct 23, 2013Granted: Aug 18, 2015
Est. expiryNov 12, 2032(~6.4 yrs left)· nominal 20-yr term from priority
Inventors:MINOWA KENICHI
H10D 86/443H10D 86/60H01L 27/1244G02F 2001/134372G02F 1/1368G02F 1/134363G02F 1/136259G02F 1/134372
38
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Cited by
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References
4
Claims

Abstract

A TFT array substrate includes: a pixel electrode, which is arranged in a pixel region formed in a matrix shape by a gate wiring and a source wiring on an insulating substrate; a switching element, which is disposed at an intersection of the gate wiring and the source wiring; a counter electrode, which is formed on the pixel electrode with interposing an insulating film; and a silicon film is formed on a lower layer so as to face the source wiring, wherein the source wiring and the pixel electrode are formed of the same transparent conductive material layer, and the source wiring and the silicon film are formed so that end faces of the source wiring and the silicon film are overlapped and a width of the source wiring is identical to a width of the silicon film, in a plan view.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A TFT array substrate employing a fringe field mode comprising:
 a pixel electrode, which is arranged in a pixel region formed in a matrix shape by a gate wiring and a source wiring on an insulating substrate; 
 a switching element, which is disposed at an intersection of the gate wiring and the source wiring; 
 a counter electrode, which is formed on the pixel electrode with an insulating film interposed therebetween; and 
 a silicon film formed on a lower layer so as to face the source wiring, 
 wherein the source wiring and the pixel electrode are formed of the same transparent conductive material layer, and 
 wherein the source wiring and the silicon film are formed so that end faces of the source wiring and the silicon film are overlapped and a width of the source wiring is identical to a width of the silicon film in a plan view; and 
 wherein the end faces of the source wiring and the silicon film are formed to be flush with one another in the plan view outside of a region corresponding to the intersection of the gate wiring and the source wiring. 
 
     
     
       2. The TFT array substrate according to  claim 1 ,
 wherein the source wiring and the silicon film are formed so that each width is identical to each other in a region, except for the region corresponding to the intersection of the gate wiring and the source wiring. 
 
     
     
       3. A liquid crystal panel, comprising
 the TFT array substrate according to  claim 1 , and 
 an opposite substrate, which is opposite to the TFT array substrate, with liquid crystal molecules being disposed between the TFT array substrate and the opposite substrate. 
 
     
     
       4. A method of manufacturing a TFT array substrate including a pixel electrode arranged in a pixel region formed in a matrix shape by a gate wiring and a source wiring on an insulating substrate, a switching element disposed at an intersection of the gate wiring and the source wiring, and a counter electrode formed on the pixel electrode via an insulating film, the method comprising:
 forming the gate wiring on the insulating substrate; 
 forming a silicon film formed in a matrix shape over the gate wiring; 
 forming the pixel electrode in the pixel region simultaneously with forming the source wiring on the silicon film of the same transparent material layer; and 
 forming the counter electrode on the pixel electrode with interposing the insulating film therebetween, 
 wherein the source wiring and the silicon film are formed so that end faces of the source wiring and the silicon film are overlapped and a width of the source wiring is identical to that of the silicon film; and 
 wherein the end faces of the source wiring and the silicon film are formed to be flush with one another in the plan view outside of a region corresponding to the intersection of the gate wiring and the source wiring.

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