Semiconductor device and information processing system having the same

Abstract

A method for accessing a plurality of DRAM devices each having a plurality of banks, the plurality of DRAM devices being interconnected to receive common address and command signals. The method includes receiving a first chip selection address and a first bank address with an active command to activate a first bank in a first DRAM device of the plurality of DRAM devices. A first bank active flag is set, corresponding to the first bank address, in the first DRAM device of the plurality of DRAM devices. A second bank address with a column command is received. A second bank is accessed in a second DRAM device of the plurality of DRAM devices having a set bank active flag corresponding to the second bank address.

What is claimed is: 
     
       1. A method for accessing a plurality of DRAM devices each having a plurality of banks, the plurality of DRAM devices being interconnected to receive common address and command signals, the method comprising:
 receiving a first chip selection address and a first bank address with an active command to activate a first bank in a first DRAM device of the plurality of DRAM devices; 
 setting a first bank active flag, corresponding to the first bank address, in the first DRAM device of the plurality of DRAM devices; 
 receiving a second bank address with a column command; and 
 accessing a second bank in a second DRAM device of the plurality of DRAM devices having a set bank active flag corresponding to the second bank address. 
 
     
     
       2. The method as claimed in  claim 1 , wherein a chip selection address is not received with the column command. 
     
     
       3. The method as claimed in  claim 1 , wherein the first bank address and the second bank address are the same. 
     
     
       4. The method as claimed in  claim 1 , wherein the column command is a read command. 
     
     
       5. The method as claimed in  claim 1 , further comprising:
 receiving a third bank address with a precharge command to precharge a third bank in each of the plurality of DRAM devices; 
 precharging the third bank in each of the plurality of DRAM devices; and 
 resetting a bank active flag corresponding to the third bank address in each of the plurality of DRAM devices. 
 
     
     
       6. The method as claimed in  claim 5 , wherein the first bank address and the third bank address are the same. 
     
     
       7. The method as claimed in  claim 1 , further comprising:
 receiving a precharge all command to precharge all banks in each of the plurality of DRAM devices; 
 precharging all banks in each of the plurality of DRAM devices; and 
 resetting bank active flags corresponding to all bank address in each of the plurality of DRAM devices. 
 
     
     
       8. The method as claimed in  claim 1 , wherein an interface device provides the address and control signals to the plurality of DRAM devices. 
     
     
       9. The method as claimed in  claim 1 , wherein the plurality of DRAM devices are provided in a stacked configuration and connected by through silicon vias. 
     
     
       10. The method as claimed in  claim 9 , wherein an interface device provides the address and control signals to the plurality of DRAM devices. 
     
     
       11. The method as claimed in  claim 10 , wherein an interposer with external terminals is provided at the bottom of the stack. 
     
     
       12. The method as claimed in  claim 9 , wherein an interposer with external terminals is provided at the bottom of the stack. 
     
     
       13. The method as claimed in  claim 1 , wherein the first chip selection address is compared to a specific chip address in each of the plurality of DRAM devices to determine the first DRAM device of the plurality of DRAM devices. 
     
     
       14. The method as claimed in  claim 13 , wherein the specific chip address in each of the plurality of DRAM devices is determined through a cascaded connection of the plurality of DRAM devices.