Differential output circuit and semiconductor device

Abstract

A highly reliable circuit is realized using the transistors having a lower withstand voltage. There are provided a differential pair including a first and a second transistor which respectively receive input signals having mutually reversed phases; a third and a fourth transistor respectively cascode-coupled to the first and the second transistor, and having the same conductivity type as the first and the second transistor; a first and a second output terminal coupled to respective drains of the third and the fourth transistor; and a voltage divider circuit which divides an intermediate potential between respective potentials of the first and the second output terminal and supplies the divided potential to gates of the third and the fourth transistor.

What is claimed is:  
     
       1. A differential output circuit comprising:
 a differential pair including a first transistor and a second transistor which respectively receive input signals having mutually reversed phases; 
 a third transistor and a fourth transistor respectively cascode-coupled to the first transistor and the second transistor, and having the same conductivity type as the first transistor and the second transistor; 
 a first output terminal and a second output terminal coupled to respective drains of the third transistor and the fourth transistor; 
 a voltage divider circuit which divides an intermediate potential between respective potentials of the first output terminal and the second output terminal and supplies the divided potential to respective gates of the third transistor and the fourth transistor; 
 two buffer circuits which supply the respective input signals to respective gates of the first transistor and the second transistor; and 
 a power supply circuit which lowers a first power supply voltage and supplies the lowered voltage to the two buffer circuits as a second power supply voltage. 
 
     
     
       2. The differential output circuit according to  claim 1 ,
 wherein the voltage divider circuit is configured to change a voltage dividing ratio when a potential of either the first or the second output terminal is within a predetermined range. 
 
     
     
       3. The differential output circuit according to  claim 1 ,
 wherein the voltage divider circuit is configured to change a voltage dividing ratio when the second power supply voltage is within a predetermined range. 
 
     
     
       4. The differential output circuit according to  claim 1 ,
 wherein a current supply forming the differential pair is activated when the first power supply voltage is within a predetermined range. 
 
     
     
       5. The differential output circuit according to  claim 4 ,
 wherein the current supply is deactivated when the second power supply voltage is not output from the power supply circuit. 
 
     
     
       6. The differential output circuits according to  claim 1 ,
 wherein the two buffer circuits are respectively AC-coupled to respective gates of the first transistor and the second transistor so as to provide respective gates of the first transistor and the second transistor with the input signals which have been offset by an amount of the second power supply voltage. 
 
     
     
       7. A differential output circuit comprising:
 a differential pair including a first transistor and a second transistor which respectively receive input signals having mutually reversed phases; 
 a third transistor and a fourth transistor respectively cascode-coupled to the first transistor and the second transistor, and having the same conductivity type as the first transistor and the second transistor; 
 a first output terminal and a second output terminal coupled to respective drains of the third transistor and the fourth transistor; 
 a voltage divider circuit which divides an intermediate potential between respective potentials of the first output terminal and the second output terminal and supplies the divided potential to respective gates of the third transistor and the fourth transistor; 
 two buffer circuits which supply the respective input signals to respective gates of the first transistor and the second transistor; and 
 a power supply circuit which lowers a first power supply voltage and supplies the lowered voltage to the two buffer circuits as a second power supply voltage, 
 wherein the voltage divider circuit is configured to change a voltage dividing ratio when the second power supply voltage is within a predetermined range. 
 
     
     
       8. The differential output circuit according to  claim 7 ,
 wherein a current supply forming the differential pair is activated when the first power supply voltage is within a predetermined range. 
 
     
     
       9. The differential output circuit according to  claim 8 ,
 wherein the current supply is deactivated when the second power supply voltage is not output from the power supply circuit. 
 
     
     
       10. The differential output circuits according to  claim 7 ,
 wherein the two buffer circuits are respectively AC-coupled to respective gates of the first transistor and the second transistor so as to provide respective gates of the first transistor and the second transistor with the input signals which have been offset by an amount of the second power supply voltage. 
 
     
     
       11. A differential output circuit comprising:
 a differential pair including a first transistor and a second transistor which respectively receive input signals having mutually reversed phases; 
 a third transistor and a fourth transistor respectively cascode-coupled to the first transistor and the second transistor, and having the same conductivity type as the first transistor and the second transistor; 
 a first output terminal and a second output terminal coupled to respective drains of the third transistor and the fourth transistor; 
 a voltage divider circuit which divides an intermediate potential between respective potentials of the first output terminal and the second output terminal and supplies the divided potential to respective gates of the third transistor and the fourth transistor; 
 two buffer circuits which supply the respective input signals to respective gates of the first transistor and the second transistor; and 
 a power supply circuit which lowers a first power supply voltage and supplies the lowered voltage to the two buffer circuits as a second power supply voltage, 
 wherein the differential pair has a current supply that is activated when the first power supply voltage is within a predetermined range. 
 
     
     
       12. The differential output circuit according to  claim 11 ,
 wherein the voltage divider circuit is configured to change a voltage dividing ratio when a potential of either the first output terminal or the second output terminal is within a predetermined range. 
 
     
     
       13. The differential output circuit according to  claim 11 ,
 wherein the voltage divider circuit is configured to change a voltage dividing ratio when the second power supply voltage is within a predetermined range. 
 
     
     
       14. The differential output circuit according to  claim 4 ,
 wherein the current supply is deactivated when the second power supply voltage is not output from the power supply circuit. 
 
     
     
       15. The differential output circuits according to  claim 1 ,
 wherein the two buffer circuits are respectively AC-coupled to respective gates of the first transistor and the second transistor so as to provide respective gates of the first transistor and the second transistor with the input signals which have been offset by an amount of the second power supply voltage.