LSI design method

Abstract

Buffers on a clock tree are reduced, as long as there is enough set-up margin, in order to reduce power consumption in the clock tree. An FF group coupled to a partial tree, which is a part of the clock tree and expanded from the branch point being focused on, is defined as the target FF and the other FFs are defined as non-target FFs. The target buffer of an elimination candidate and the target and non-target FFs are defined so as not to change the slack in principle in a signal propagation path between the non-target FFs even if the buffer is eliminated. The buffer which can be eliminated is specified within a range in each signal propagation path which has a start point at the non-target FF and an end point at the target FF and in each signal propagation path between the target FFs.

What is claimed is: 
     
       1. An LSI design method for a clock tree including a plurality of buffers between a clock generation source and a plurality of timing definition circuits, the LSI design method comprising:
 using a computer to perform the steps of:
 defining one or more target buffers which exists between one branch point in the clock tree and a next branch point in one branch extending from the one branch point toward the timing definition circuits; 
 defining the timing definition circuits, which are coupled to terminals of a partial clock tree expanding from the one branch, as target timing definition circuits; 
 defining the timing definition circuits except the target timing definition circuits as non-target timing definition circuits; and 
 eliminating one or more of the target buffers which reduces a set-up margin in at least one signal propagation path having a start point at one of the non-target timing definition circuits and an end point at one of the target timing definition circuits while maintaining set up margins to be greater than or equal to zero in all the signal propagation paths having a start point at one of the non-target timing definition circuits and an end point at one of the target timing definition circuits. 
 
 
     
     
       2. The LSI design method according to  claim 1 , further comprising:
 using the computer to further perform the step of:
 adjusting the set-up margin to be equal to or greater than zero or more in all the signal propagation paths between the timing definition circuits, before the step of eliminating the one or more of the target buffers. 
 
 
     
     
       3. The LSI design method according to  claim 1 ,
 wherein each of the branch points in the clock tree are selected sequentially as the one branch point, 
 all the branches extending from the one branch point are selected sequentially as the next branch point, and 
 the step of eliminating the one or more target buffers is performed for each sequentially selected one branch point and next branch point. 
 
     
     
       4. The LSI design method according to  claim 3 ,
 wherein one of the branch points closest to the clock generation source is selected first as the one branch point. 
 
     
     
       5. The LSI design method according to  claim 3 , further comprising:
 using the computer to further perform the step of:
 defining the branch of an exclusion target before eliminating the one or more target buffers, and 
 
 wherein the step of eliminating the one or more target buffers is skipped and moved to the next branch point, when the target buffers are included in the branch of the exclusion target. 
 
     
     
       6. The LSI design method according to  claim 5 ,
 wherein the branch, which is located in a path having the smallest margin for an electrical design rule in the clock tree, is defined as the branch of the exclusion target. 
 
     
     
       7. The LSI design method according to  claim 5 ,
 wherein the branch, which does not include one or more of the buffers, in the clock tree, is defined as the branch of the exclusion target. 
 
     
     
       8. The LSI design method according to  claim 1 ,
 wherein design data after placement and routing is used. 
 
     
     
       9. The LSI design method according to  claim 8 , further comprising:
 using the computer to further perform the step of:
 after executing the step of eliminating the one or more target buffers, routing for a wiring from the one of the buffers, which drove an input of the eliminated one or more target buffers, to the one of the buffers which was driven by the eliminated one or more target buffers, and a capacitance and a resistance of the wiring are extracted and a delay value of the one of the buffers which drove the input of the eliminated one or more target buffers is calculated on the basis of the capacitance and the resistance. 
 
 
     
     
       10. The LSI design method according to  claim 1 ,
 wherein each of the timing definition circuit is one of a flip-flop, a latch, a clock-synchronous type memory, or a gate for clock gating.