System, method and computer-accessible medium for design for testability support for launch and capture of power reduction in launch-off-capture testing

Abstract

Exemplary system, method and computer accessible medium that can transform a circuit by selecting at least one scan cell as an interface register and inserting a shadow register into each interface register. Operations can be shifted to load and unload at least one scan cell in the circuit. An operation can be launched in at least one of the interface registers and in a first set of scan cells. A capture operation can be performed in a second set of scan cells. An operation can be restored in at least one interface register by transferring data from at least one shadow register.

What is claimed is: 
     
       1. A non-transitory computer-accessible medium having stored thereon computer-executable instructions for modifying at least one circuit, wherein, when a computer hardware arrangement executes the instructions, the computer arrangement is configured to perform procedures comprising:
 dividing the at least one circuit into a plurality of regions such that each scan cell of a plurality of scan cells belongs to a single region, and the regions do not form a cycle; 
 levelizing the regions; 
 selecting a set of the scan cells of at least one first region that drive a plurality of interface registers that belong to at least one second region as at least one interface register; and 
 inserting at least one shadow register into the at least one interface register. 
 
     
     
       2. The non-transitory computer readable medium of  claim 1 , wherein the computer arrangement is further configured to shift operations to load and unload the scan cells. 
     
     
       3. The non-transitory computer readable medium of  claim 2 , wherein the computer arrangement is further configured to:
 launch an operation in at least one of the at least one interface register or a second set of the scan cells; and 
 perform a capture operation in a third set of the scan cells. 
 
     
     
       4. The non-transitory computer readable medium of  claim 3 , wherein the computer arrangement is further configured to perform a restore operation in the at least one interface register by transferring data from the at least one shadow register into the at least one interface register. 
     
     
       5. The non-transitory computer readable medium of  claim 4 , wherein the computer arrangement is further configured to repeat the launch, perform and restore procedures until all scan cells have been captured at least once. 
     
     
       6. The non-transitory computer readable medium of  claim 3 , wherein the computer arrangement is further configured to perform the launch procedure and the capture procedure for each region one at a time. 
     
     
       7. The non-transitory computer readable medium of  claim 6 , wherein the computer arrangement is further configured to perform the launch procedure and the capture procedure for transitions within each region. 
     
     
       8. The non-transitory computer readable medium of  claim 4 , wherein the computer arrangement is further configured to perform the launch procedure and the capture procedure after the restoring procedure depending on a level of a region. 
     
     
       9. The non-transitory computer readable medium of  claim 1 , wherein the computer arrangement is further configured to perform a partitioning procedure to stagger launch-capture clocks of the regions. 
     
     
       10. The non-transitory computer readable medium of  claim 9 , wherein the computer arrangement is further configured to perform the partitioning procedure based on at least one constraint and at least two optimization criteria. 
     
     
       11. The non-transitory computer readable medium of  claim 10 , wherein the at least two optimization criteria includes a minimization of launch and capture power, and a minimization of the interface registers. 
     
     
       12. The non-transitory computer readable medium of  claim 1 , wherein the regions are acyclical. 
     
     
       13. The non-transitory computer readable medium of  claim 1 , wherein the computer arrangement is further configured to load a test pattern into at least one of the scan cells. 
     
     
       14. A method for transforming a circuit comprising:
 dividing the at least one circuit into a plurality of regions such that each scan cell of a plurality of scan cells belongs to a single region, and the regions do not form a cycle; 
 levelizing the regions; 
 selecting a set of the scan cells of at least one first region that drive a plurality of interface registers that belong to at least one second region as at least one interface register; and 
 using a computer hardware arrangement, inserting at least one shadow register into the at least one interface register. 
 
     
     
       15. The method of  claim 14 , further comprising performing shifting operations to load and unload the scan cells. 
     
     
       16. A circuit comprising:
 a plurality of levelized regions such that each scan cell of a plurality of scan cells belongs to a single region, and the regions do not form a cycle; 
 a set of the scan cells of at least one first region that drive a plurality of interface registers that belong to at least one second region, wherein the set of scan cells are selected as at least one interface register; and 
 at least one shadow register for the at least one interface register. 
 
     
     
       17. The circuit of  claim 16 , wherein the at least one scan cell is configured to be loaded and unloaded using a shift operations. 
     
     
       18. The circuit of  claim 16 , further comprising at least one test pattern loaded into at least on of the scan cells. 
     
     
       19. The method of  claim 18 , wherein the computer arrangement is further configured to:
 launch an operation in at least one of the at least one interface register or a second set of the scan cells; and 
 perform a capture operation in a third set of the scan cells. 
 
     
     
       20. The method of  claim 19 , further comprising performing a restore operation in the at least one interface register by transferring data from the at least one shadow register into the at least one interface register.