Electrostatic discharge clamping devices with tracing circuitry

Abstract

Techniques and architectures corresponding to electrostatic discharge clamping circuits with tracing circuitry are described.

The invention claimed is: 
     
       1. An electrostatic discharge (ESD) protection circuit arrangement comprising:
 at least one MOS buffer transistor configured to receive an input signal from a first functional circuit block at a gate of the at least one MOS buffer transistor and to provide a first portion of an output signal to a second functional circuit block; 
 a leakage current prevention circuit comprising: 
 at least one MOS clamping transistor coupled to the at least one MOS buffer transistor; and 
 at least one MOS tracing circuitry coupled to the at least one MOS clamping transistor, the at least one MOS tracing circuitry having at least one MOS tracing transistor configured to control a voltage at a gate of the at least one MOS clamping transistor; 
 wherein at least one of a source or a drain of the at least one MOS clamping transistor or the at least one MOS tracing transistor is coupled to a first supply voltage, and 
 wherein the at least one MOS tracing transistor of a first MOS tracing circuitry comprises a first MOS tracing transistor and a second MOS tracing transistor coupled to the first MOS tracing transistor, and wherein the first MOS tracing transistor and the second MOS tracing transistor being transistors of a first MOS type. 
 
     
     
       2. The ESD protection circuit arrangement of  claim 1 , wherein the at least one MOS clamping transistor comprises a first MOS clamping transistor being a transistor of the first MOS type. 
     
     
       3. The ESD protection circuit arrangement of  claim 2 , wherein the at least one MOS tracing transistor of a second MOS tracing circuit comprises a third MOS tracing transistor and a fourth MOS tracing transistor coupled to the third MOS tracing transistor, and wherein the third MOS tracing transistor and the fourth MOS tracing transistor being transistors of a second MOS type. 
     
     
       4. The ESD protection circuit arrangement of  claim 3 , wherein the at least one MOS clamping transistor comprises a second MOS clamping transistor being a transistor of a second MOS type, and wherein at least one of a source or a drain of the second MOS clamping transistor is coupled to a second supply voltage. 
     
     
       5. The ESD protection circuit arrangement of  claim 4 , further comprising a switch coupled to at least one of a source or a drain of the fourth MOS tracing transistor, and wherein the switch is operable to couple the at least one of a source or a drain of the fourth MOS clamping transistor to an external supply voltage. 
     
     
       6. The ESD protection circuit arrangement of  claim 5 , wherein the second supply voltage and the external supply voltage are negative supply voltages. 
     
     
       7. The ESD protection circuit arrangement of  claim 4 , wherein the first MOS type and the second MOS type are of a same MOS type and is at least one of a PMOS or NMOS. 
     
     
       8. The ESD protection circuit arrangement of  claim 4 , wherein the first MOSS type is a PMOS and the second MOS type is a NMOS. 
     
     
       9. The ESD protection circuit arrangement of  claim 4 , wherein the first MOS type transistor is a NMOS and the second MOS type is a PMOS. 
     
     
       10. The ESD protection circuit arrangement of  claim 1 , wherein a gate and at least one of a drain or a source of the at least one MOS tracing transistor is coupled to a central node that is coupled to the gate of the at least one MOS clamping transistor. 
     
     
       11. The ESD protection circuit arrangement of  claim 10 , wherein a body terminal of the at least one MOS tracing transistor and a body terminal of the at least one MOS clamping transistor are coupled to the central node. 
     
     
       12. The ESD protection circuit arrangement of  claim 1 , further comprising a switch coupled to at least one of a source or a drain of the first MOS tracing transistor, and wherein the switch is operable to couple the at least one of a source or drain of the first MOS clamping transistor to an external supply voltage. 
     
     
       13. The ESD protection circuit arrangement of  claim 12 , wherein the first supply voltage and the external supply voltage are positive supply voltages. 
     
     
       14. The ESD protection circuit arrangement of  claim 1 , wherein the at least one MOS clamping transistor and the at least one MOS tracing transistor are coupled to an impedance device. 
     
     
       15. A method for electrostatic discharge (ESD) protection comprising;
 providing an interface circuit between a first functional circuit block and a second functional circuit block for sending an output signal corresponding to an input signal from the first functional circuit block to the second functional circuit block; 
 providing a buffer circuitry and a leakage current prevention circuitry in the interface circuit; 
 providing at least one tracing circuitry and at least one MOS clamping transistor in the leakage current prevention circuitry; 
 coupling the second functional circuit block to a power source; 
 de-coupling the second functional circuit block from the power source; 
 maintaining, by the at least one tracing circuitry, a voltage at a gate of at least one MOS clamping transistor below its threshold voltage, during the coupling or de-coupling; 
 upon receiving an electrostatic discharge voltage at the interface circuit, dissipating the electrostatic discharge voltage by the at least one MOS clamping transistor. 
 
     
     
       16. The method of  claim 15 , wherein maintaining, by the at least one tracing circuitry, a voltage at a gate of at least one MOS clamping transistor below its threshold voltage, during the coupling or de-coupling comprising:
 maintaining a voltage at a gate of a MOS clamping transistor of a first type below its threshold voltage by a first tracing circuitry of the at least one tracing circuitry; and 
 maintaining a voltage at a gate of a MOS clamping transistor of a second type below its threshold voltage by a second tracing circuitry of the at least one tracing circuitry. 
 
     
     
       17. The method of  claim 16 , wherein the voltage of the gate of the MOS clamping transistor of the first type, the voltage of the gate of the MOS clamping transistor of the second type, or a combination thereof, are in a sub-threshold region.