Device and method to perform a parallel memory test

Abstract

The invention relates to a semiconductor device including N memory modules, N being greater than or equal to three, each module having an array of memory cells arranged in rows and columns, a write circuit coupled to each module and configured to write data in the memory cells, a read circuit coupled to each module and configured to supply output data from the memory cells, a module selection circuit configured to individually select one memory module in a regular operation mode, and to collectively select two or more of the modules in a parallel mode, and a comparator circuit coupled to the N modules and configured to compare, in the parallel mode, the output data supplied by the N modules.

The invention claimed is:  
     
       1. Semiconductor device comprising:
 N memory modules, modules, N being greater than or equal to three, each module comprising an array of memory cells arranged in rows and columns, 
 a write circuit coupled to each module and configured to write data in the memory cells, 
 a read circuit coupled to each module and configured to supply output data from the memory cells, 
 a module selection circuit configured to individually select one memory module in a regular operation mode, and to collectively select two or more of the modules in a parallel mode, and 
 a comparator circuit coupled to the N modules and configured to compare, in the parallel mode, the output data supplied by at least two of the N modules, wherein: 
 the N memory modules comprise one module designated as the reference module and N−1 modules designated as auxiliary modules, 
 the comparator circuit is configured to compare the output data supplied by each auxiliary module with the output data supplied by the reference module, and 
 the semiconductor device is configured to supply the output data from the reference module to a data verification means. 
 
     
     
       2. Device according to  claim 1 , further comprising a circuit configured to perform a cyclical redundancy check on the output data supplied by the reference module, and to supply a check result to the data verification means. 
     
     
       3. Device according to  claim 1 , wherein the verification means is built-in self test circuit coupled to the module selection circuit, the comparator circuit, and to the reference module. 
     
     
       4. Device according to  claim 1 , wherein the comparator circuit further comprises means to enable and disable a comparison of output data supplied by an auxiliary module with the output data supplied by the reference module, depending on the status of a module select signal. 
     
     
       5. Device according to  claim 1 , wherein at least two of the memory modules comprise different numbers of rows of memory cells, and the memory module comprising the greatest number of rows is designated as the reference array. 
     
     
       6. Device according to  claim 5 , wherein the module selection circuit is configured to:
 receive on input a parallel signal and a module signal, 
 supply on output N module select signals, one signal per module, and 
 deselect one or more select signals regardless of the state of the parallel signal. 
 
     
     
       7. Method of testing N memory modules in parallel, N being greater than or equal to three, comprising the steps of:
 writing an input data at an address in each of the memory modules, 
 reading the data at the address of the modules to obtain output data, 
 determining whether the output data from the modules are identical, 
 
       wherein:
 designating one of the modules as the reference module and the N−1 other modules as auxiliary modules, 
 comparing the output data from each of the auxiliary modules being tested with the output data from the reference module, and 
 supplying the output data from the reference module to a data verification means. 
 
     
     
       8. Method according to  claim 7 , comprising the steps of:
 determining the largest memory module, and 
 designating the largest memory module as the reference module. 
 
     
     
       9. Method according to  claim 8 , further comprising, during a parallel operation, the step of selecting a subset of at least two of the N memory modules according to an address belonging to a test space common to the subset of modules.