Method of fabricating a single photon avalanche diode imaging sensor

Abstract

A method of fabricating an avalanche photodiode pixel includes growing a second doped semiconductor layer on a first doped semiconductor layer having a first doping concentration. The second doped semiconductor layer is grown with a second doping concentration and is of an opposite majority charge carrier type as the first doped semiconductor layer. A doped contact region having a third doping concentration is formed in the second doped semiconductor layer between the doped contact region and the first doped semiconductor layer. The doped contact region is of a same majority charge carrier type as the second doped semiconductor layer. The third doping concentration is greater than the second doping concentration. A guard ring region is formed in the second doped semiconductor layer, is of an opposite majority charge carrier type as the second doped semiconductor layer, and extends through the second doped semiconductor layer surrounding the doped contact region.

What is claimed is: 
     
       1. A method of fabricating an avalanche photodiode pixel, the method comprising:
 growing a second doped semiconductor layer on a first doped semiconductor layer having a first doping concentration, wherein the second doped semiconductor layer is grown with a second doping concentration, and wherein the second doped semiconductor layer is of an opposite majority charge carrier type as the first doped semiconductor layer; 
 forming a doped contact region having a third doping concentration in the second doped semiconductor layer, wherein the second doped semiconductor layer is disposed between the doped contact region and the first doped semiconductor layer, and wherein the doped contact region is of a same majority charge carrier type as the second doped semiconductor layer, and wherein the third doping concentration is greater than the second doping concentration; and 
 forming a guard ring region in the second doped semiconductor layer, wherein the guard ring region is of an opposite majority charge carrier type as the second doped semiconductor layer, and wherein the guard ring region extends entirely through the second doped semiconductor layer and surrounds the doped contact region. 
 
     
     
       2. The method of  claim 1 , further comprising attaching a logic wafer to the second doped semiconductor layer, wherein the second doped semiconductor layer is disposed between the first doped semiconductor layer and the logic wafer. 
     
     
       3. The method of  claim 1 , further comprising thinning the first doped semiconductor layer to a thickness that is less than an original thickness, wherein the thickness is such that photons incident on a multiplication junction defined at an interface between the first doped semiconductor layer and the second doped semiconductor layer are converted to a measurable electric current. 
     
     
       4. The method of  claim 1 , further comprising:
 forming an antireflection coating disposed on the first doped semiconductor layer; and 
 forming a microlens layer, wherein the antireflection coating is disposed between the first doped semiconductor layer and the microlens layer. 
 
     
     
       5. The method of  claim 4 , further comprising forming a color filter layer, wherein the color filter layer is disposed between the antireflection coating and the microlens layer. 
     
     
       6. The method of  claim 1 , wherein the first doped semiconductor layer is p-type, the second doped semiconductor layer is n-type, and the doped contact region is n-type. 
     
     
       7. The method of  claim 1 , wherein the first doped semiconductor layer is n-type, the second doped semiconductor layer is p-type, and the doped contact region is p-type. 
     
     
       8. The method of  claim 1 , wherein the guard ring region is separated from the doped contact region in the second doped semiconductor layer by a lateral distance. 
     
     
       9. The method of  claim 1 , further comprising forming a second doped contact region within the guard ring region, wherein the second doped contact region is of a same majority charge carrier type as the guard ring region, and wherein a doping concentration of the second doped contact region is greater than a doping concentration of the guard ring region. 
     
     
       10. The method of  claim 1 , wherein the first and second doped semiconductor layers are formed by epitaxial growth, and wherein the first and second doped semiconductor layers are grown on a substrate. 
     
     
       11. A method of image sensor system fabrication, the method comprising:
 forming a first doped semiconductor layer on a substrate, wherein the first doped semiconductor layer is grown with a first doping concentration; 
 forming a second doped semiconductor layer on the first doped semiconductor layer, wherein the second doped semiconductor layer is grown with a second doping concentration, and wherein the second doped semiconductor layer is of an opposite majority charge carrier type as the first doped semiconductor layer; 
 forming a plurality of avalanche photodiode pixels, wherein the plurality of avalanche photodiode pixels include a doped contact region disposed in the second doped semiconductor layer, and wherein the doped contact region is of a same majority charge carrier type as the second doped semiconductor layer and has a greater doping concentration than the second doped semiconductor layer; 
 forming a guard ring region which extends entirely through the second doped semiconductor layer, wherein the guard ring region is of an opposite majority charge carrier type as the second doped semiconductor layer, and wherein the guard ring region separates individual pixels in the plurality of avalanche photodiode pixels; and 
 connecting a logic wafer to the second doped semiconductor layer, wherein the second doped semiconductor layer is disposed between the logic wafer and the first doped semiconductor layer. 
 
     
     
       12. The method of  claim 11 , further comprising:
 forming an antireflection coating disposed on the first doped semiconductor layer; and 
 forming a microlens layer, wherein the antireflection coating is disposed between the first doped semiconductor layer and the microlens layer. 
 
     
     
       13. The method of  claim 12 , further comprising forming a color filter layer, wherein the color filter layer is disposed between the antireflection coating and the microlens layer. 
     
     
       14. The method of  claim 11 , further comprising forming control circuitry and readout circuitry, wherein the control circuitry is coupled to control operation of the plurality of avalanche photodiode pixels, and wherein the readout circuitry is coupled to readout image data from the plurality of avalanche photodiode pixels. 
     
     
       15. The method of  claim 14 , further comprising forming function logic coupled to the readout circuitry, to store image data read out from the plurality of avalanche photodiode pixels. 
     
     
       16. The method of  claim 14 , wherein the logic wafer includes the control circuitry and the readout circuitry. 
     
     
       17. The method of  claim 11 , wherein the plurality of avalanche photodiode pixels are arranged into an imaging array comprising rows and columns. 
     
     
       18. The method of  claim 11 , further comprising removing the substrate and thinning the first doped semiconductor layer to a thickness that is less than an original thickness, wherein the thickness is such that photons incident on a multiplication junction defined at an interface between the first doped semiconductor layer and the second doped semiconductor layer are converted to a measurable electric charge. 
     
     
       19. The method of  claim 11 , further comprising forming a quenching element coupled to the individual pixels in the plurality of avalanche photodiode pixels to quench avalanching by lowering a bias voltage. 
     
     
       20. The method of  claim 11 , further comprising forming a second doped contact region within the guard ring region, wherein the second doped contact region is of a same majority charge carrier type as the guard ring region, and wherein a doping concentration of the second doped contact region is greater than a doping concentration of the guard ring region. 
     
     
       21. The method of  claim 11 , wherein the first and second doped semiconductor layers are formed by epitaxial growth. 
     
     
       22. The method of  claim 11 , wherein the substrate comprises one of silicon, silicon oxide, metal oxide, SiGe, Ge, or InGaAsP. 
     
     
       23. The method of  claim 11 , wherein the first semiconductor layer is passivated by dopant implantation in the first semiconductor layer or by growth of a charged oxide layer on the first semiconductor layer.