System and method of electromigration mitigation in stacked IC designs

Abstract

A computer implemented method comprises accessing a 3D-IC model stored in a tangible, non-transitory machine readable medium, processing the model in a computer processor to generate a temperature map containing temperatures at a plurality of points of the 3D-IC under the operating condition; identifying an electromigration (EM) rating factor, and calculating and outputting from the processor data representing a temperature-dependent EM current constraint at each point.

What is claimed is: 
     
       1. A computer implemented method comprising:
 accessing a three-dimensional integrated circuit (3D-IC) model stored in a tangible, non-transitory machine readable medium, the model comprising a plurality of elements representing a 3D-IC design to be fabricated and to operate under a condition; 
 processing the 3D-IC model in a computer processor, wherein the processor is programmed to analyze the 3D-IC to calculate a temperature at each of a plurality of points of the 3D-IC operating under the condition; 
 identifying a respective electrical resistance at each of the plurality of points based on the calculated temperatures; 
 calculating and outputting from the processor data representing temperature-dependent power consumption at each of the plurality of points of the 3D-IC based on the temperature at each of the plurality of points and the respective electrical resistance at each of the plurality of points; 
 identifying a potential electromigration violation based on the temperature-dependent power consumption at each of the plurality of points of the 3D-IC, wherein an indicator representing the potential electromigration violation at a corresponding location is output, when a power index representing power consumption at a corresponding location is higher than an assigned power budget at the corresponding location; and 
 changing the 3D-IC design to mitigate the potential electromigration violation. 
 
     
     
       2. The method of  claim 1 , further comprising
 identifying an electromigration (EM) rating factor at each of the plurality of points of the 3D-IC; and 
 outputting data representing a temperature-dependent electromigration (EM) current constraint at each of the plurality of points of the 3D-IC based on the electromigration (EM) rating factors, 
 wherein 
 the EM rating factor at each of the plurality of points is calculated based on an EM performance capability of a point at a temperature relative to the EM capability at a reference temperature, the EM performance capability of a point at a temperature being calculated based on the temperature and a current density of the point; and 
 the temperature-dependent EM current constraint at one of the points of the 3D-IC is obtained based on the corresponding electromigration rating factor and an electromigration constraint at a reference temperature. 
 
     
     
       3. The method of  claim 2 , wherein the temperature-dependent electromigration current constraint at one of the points of the 3D-IC is obtained by multiplying the corresponding electromigration rating factor and an electromigration constraint at a reference temperature. 
     
     
       4. The method of  claim 2 , further comprising:
 identifying a potential electromigration violation by analyzing electromigration on the 3D-IC by applying the temperature-dependent electromigration current constraint, and 
 outputting from the processor an indicator representing the potential electromigration violation at a corresponding location. 
 
     
     
       5. The method of  claim 4 , wherein the indicator is output when the analyzing determines that a current at one point of the 3D-IC is higher than the temperature-dependent electromigration current constraint. 
     
     
       6. The method of  claim 1 , wherein the 3D-IC design is changed by spreading a clock distribution network out to increase a spacing between at least two cells in the clock distribution network, or by adjusting a pitch of a power mesh in the 3D-IC. 
     
     
       7. The method of  claim 1 , wherein the 3D-IC design is changed based on temperature-dependent power consumption at each of the plurality of points. 
     
     
       8. The method of  claim 7 , wherein the 3D-IC design is changed by distributing and changing clock cells in the 3D-IC design. 
     
     
       9. The method of  claim 1 , further comprising outputting from the processor the changed 3D-IC design to a persistent storage medium, for fabricating a set of photomasks for the 3D-IC. 
     
     
       10. The method of  claim 9 , further comprising:
 fabricating a set of photomasks for the changed 3D-IC design and fabricating a 3D-IC according to the changed 3D-IC design. 
 
     
     
       11. The method of  claim 1 , further comprising:
 calculating and outputting from the processor data representing a voltage drop at each point of the plurality of points based on the electrical resistance. 
 
     
     
       12. A computer implemented method comprising:
 accessing a three-dimensional integrated circuit (3D-IC) model stored in a tangible, non-transitory machine readable medium, the model comprising a plurality of elements representing a 3D-IC design to be fabricated and to operate under a condition; 
 processing the 3D-IC model in a computer processor, wherein the processor is programmed to analyze the 3D-IC to calculate a temperature at each of a plurality of points of the 3D-IC operating under the condition; 
 identifying a respective electrical resistance at each of the plurality of points based on the calculated temperatures; and 
 calculating and outputting from the processor data representing temperature-dependent power consumption at each of the plurality of points of the 3D-IC based on the electrical resistance; 
 identifying a potential electromigration violation based on the temperature-dependent power consumption at each of the plurality of points of the 3D-IC, wherein an indicator representing the potential electromigration violation at a corresponding location is output, when a power index representing power consumption at a corresponding location is higher than an assigned power budget at the corresponding location; and 
 changing the 3D-IC design to mitigate the potential electromigration violation. 
 
     
     
       13. The method of  claim 12 , wherein
 the 3D-IC design is changed based on temperature-dependent power consumption at each of the plurality of points. 
 
     
     
       14. The method of  claim 12 , further comprising outputting from the processor the changed 3D-IC design to a persistent storage medium, for fabricating a set of photomasks for the 3D-IC. 
     
     
       15. A computer implemented system comprising:
 one or more processors; and 
 at least one tangible, non-transitory machine readable medium encoded with one or more programs, to be executed by one of the one or more processors, to perform steps of: 
 accessing a three-dimensional integrated circuit (3D-IC) model stored in a tangible, non-transitory machine readable medium, the model comprising a plurality of elements representing a 3D-IC design to be fabricated and to operate under a condition; 
 processing the 3D-IC model in the one processor, wherein the one processor is programmed to analyze the 3D-IC to calculate a temperature at each of a plurality of points of the 3D-IC operating under the condition; 
 identifying a respective electrical resistance at each of the plurality of points based on the calculated temperatures; 
 calculating and outputting from the processor data representing temperature-dependent power consumption at each of the plurality of points of the 3D-IC based on the temperature at each of the plurality of points and the respective electrical resistance at each of the plurality of points; 
 identifying a potential electromigration violation based on the temperature-dependent power consumption at each of the plurality of points of the 3D-IC, wherein an indicator representing the potential electromigration violation at a corresponding location is output, when a power index representing power consumption at a corresponding location is higher than an assigned power budget at the corresponding location; and 
 changing the 3D-IC design to mitigate the potential electromigration violation. 
 
     
     
       16. The system of  claim 15 , wherein the 3D-IC design is changed and optimized based on the data representing temperature-dependent power consumption at each of the plurality of points of the 3D-IC. 
     
     
       17. The system of  claim 15 , wherein the function of the one or more programs further comprises:
 outputting from the one processor the changed 3D-IC design to a persistent storage medium, for fabricating a set of photomasks for the 3D-IC. 
 
     
     
       18. The system of  claim 15 , wherein the function of the one or more programs further comprises:
 calculating and outputting from the processor data representing a voltage drop at each point of the plurality of points based on the electrical resistance.