Interpolation circuit for interpolating a first and a second microphone signal

Abstract

An interpolation circuit for interpolating a first and a second microphone signal and for generating an interpolated microphone signal includes a first input ( 100 ) for receiving the first microphone signal (am), a second input ( 101 ) for receiving the second microphone signal (am+1), an output ( 102 ) for outputting the interpolated microphone signal (s), a control input ( 103 ) for receiving a control signal (r), and a first circuit branch ( 104 ) including first ( 105 ) and second ( 106 ) inputs coupled to the first ( 100 ) and the second ( 101 ) input, respectively, of the interpolation circuit, and an output ( 107 ) coupled to the output ( 102 ) of the interpolation circuit, wherein the first circuit branch is provided with a means ( 108 ) for power-specific summing of the signals supplied to the first and second inputs of the first circuit branch and for outputting a power-specific summation signal at the output ( 107 ) of the first circuit branch ( 104 ).

The invention claimed is: 
     
       1. An interpolation circuit for interpolating a first and a second microphone signal and for generating an interpolated microphone signal, comprising:
 a first input for receiving the first microphone signal, 
 a second input for receiving the second microphone signal, 
 an output for outputting the interpolated microphone signal, 
 a first circuit branch having first and second inputs coupled to the first and second inputs, respectively, of the interpolation circuit, and an output coupled to the output of the interpolation circuit, the first circuit branch being provided with a means for power-specific summation of the signals supplied at the first and second inputs of the first circuit branch and for outputting a power-specific summation signal at the output of the first circuit branch, wherein the interpolation circuit is further provided with: 
 a control input for receiving a control signal, 
 a second circuit branch having a first and a second input coupled to the first and second inputs, respectively, of the interpolation circuit, and an output coupled to the output of the interpolation circuit, 
 in that the outputs of the first and second circuit branches are coupled to respective inputs of a signal combination circuit and an output of the signal combination circuit is coupled to the output of the interpolation circuit, 
 in that the second circuit branch is provided with a first multiplication circuit and a second multiplication circuit having inputs coupled to the first and second input of the second circuit branch, respectively, and outputs coupled to respective inputs of a second signal combination circuit whose output is coupled to the output of the second circuit branch, 
 in that the first and second multiplication circuits are provided with a control input coupled to the control input of the interpolation circuit and are adapted to multiply the signals supplied to them by respective first and second multiplication quantities, said first and second multiplication quantities being dependent on the control signal. 
 
     
     
       2. The interpolation circuit as claimed in  claim 1 , wherein the first and second microphone signals and the interpolated microphone signal are microphone signals converted into the frequency range, the interpolation circuit further being provided with third and fourth multiplication circuits having inputs coupled to the outputs of the first and second circuit branches, respectively, and an output coupled to the output of the interpolation circuit, in that the third and fourth multiplication circuits are adapted to multiply the signals supplied to them by frequency-dependent multiplication quantities. 
     
     
       3. The interpolation circuit as claimed in  claim 2 , wherein the frequency-dependent multiplication quantities are equal to 1−c(k) and c(k), respectively, wherein k is a frequency parameter, and in that c(k) satisfies the condition that it is a constant preferably equal to 1 for k=0 and decreases for increasing values of k until c(k) is equal to zero for higher values of k. 
     
     
       4. The interpolation circuit as claimed in  claim 1 , wherein the two microphone signals are derived from two juxtaposed microphones arranged on a circle ring in a horizontal plane, and with r satisfying the following conditions:
 for φ=φ m  is a constant, preferably equal to 0, with r increasing for values of φ passing from φ m  to φ m+1  until r is a constant, preferably equal to 1, for φ=φ m+1 , 
 wherein φ m  and φ m+1  are the corner positions of the two microphones on the circle ring and φ is a corner variable indicating the corner position of a virtual microphone assumed to be arranged on the circle ring between the two microphones, and the interpolated microphone signal at the output of the interpolation circuit is assumed to be the output signal of this virtual microphone. 
 
     
     
       5. The interpolation circuit as claimed in  claim 4 , wherein
     r=A *(φ−φ m )/(φ m+1 −φ m ),
 
 wherein A is a constant preferably equal to 1. 
 
     
     
       6. The interpolation circuit as claimed in  claim 4 , wherein f satisfies the following conditions:
 f=r B , wherein B is a constant greater than zero, preferably equal to 1. 
 
     
     
       7. The interpolation circuit as claimed in  claim 1 , wherein the means for power-specific summation includes:
 a calculation unit 
 a multiplication circuit 
 a signal combination unit ( 230 ), 
 in that the inputs of the means are coupled to respective first and second inputs of the calculation unit, an output of the calculation unit is coupled to a first input of the multiplication circuit, a first input of the means is coupled to a second input of the multiplication circuit, in that an output of the multiplication circuit is coupled to a first input of the signal combination unit, a second input of the means is coupled to a second input of the signal combination unit, and an output of the signal combination unit is coupled to the output of the means, in that the calculation unit is adapted to derive a multiplication factor (m(k)) in dependence on the signals at the inputs of the calculation unit. 
 
     
     
       8. The interpolation circuit as claimed in  claim 7 , wherein the means for power-specific summation further includes a second multiplication circuit provided with a first input coupled to the second input of the means, an output coupled to the first input of the signal combination unit, and a second input coupled to a second output of the calculation unit, and in that the calculation unit is further adapted to derive a second multiplication factor (m 2 (k)) in dependence on the signals at the inputs of the calculation unit and to supply this second multiplication factor to the second output. 
     
     
       9. The interpolation circuit as claimed in  claim 1 , wherein the first circuit branch is further provided with a fifth multiplication circuit coupled between the first input of the first circuit branch and a first input of the means for power-specific summation, and a sixth multiplication circuit coupled between the second input ( 106 ) of the first circuit branch and a second input of the means for power-specific summation. 
     
     
       10. The interpolation circuit as claimed in  claim 9 , wherein the fifth multiplication circuit is adapted to multiply the signal at its input by a multiplication factor equal to (1−g) 1/2 , and the sixth multiplication circuit is adapted to multiply the signal at its input by a multiplication factor equal to g 1/2 . 
     
     
       11. The interpolation circuit as claimed in  claim 10 , wherein g satisfies the following conditions:
 g=r C , wherein C is a constant greater than zero, preferably equal to 1. 
 
     
     
       12. The interpolation circuit as claimed in  claim 10 , wherein g satisfies the following conditions:
 g=sin D (r*π/2), wherein D is a constant greater than zero. 
 
     
     
       13. The interpolation circuit as claimed in  claim 1 , wherein the means for power-specific summation includes:
 a calculation unit 
 a multiplication circuit 
 a signal combination unit, 
 in that the inputs of the means are coupled to respective first and second inputs of the calculation unit, an output of the calculation unit is coupled to a first input of the multiplication circuit, a first input of the means is coupled to a first input of the signal combination unit, a second input of the means is coupled to a second input of the signal combination unit, and an output of the signal combination unit is coupled to a second input of the multiplication circuit, in that the calculation unit is adapted to derive a multiplication factor (m S (k)) in dependence on signals at the inputs of the calculation unit.