Apparatus and method for compressing a memory address

Abstract

An apparatus and method for converting between a full memory address and a compressed memory address. For example, one embodiment comprises one or more translation tables having a plurality of translation entries, each translation entry identifiable with a pointer value and storing a portion of a full memory address usable within the processor to address data and instructions; and address translation logic to use the translation tables to convert between the full address and a compressed version of the full address, the compressed version of the full address having the pointer value substituted for the portion of the full memory address, wherein a first portion of the processor performs operations using the compressed version of the full address and a second portion of the processor performs operations using the full address.

What is claimed is: 
     
       1. A processor comprising:
 logic to generate one or more translation tables having a plurality of translation entries, each translation entry to include a pointer value and to store a portion of a full memory address usable within the processor to address data and instructions, wherein the translation tables comprise a first translation table and a second translation table, the first and second translation tables being located at different processor pipeline stages, and wherein the first translation table is used for converting from full memory addresses to compressed memory addresses, and the second translation table is used for converting from compressed memory addresses to full memory addresses; and 
 address translation logic to use the translation tables to convert between the full address and a compressed version of the full address, the compressed version of the full address having the pointer value substituted for the portion of the full memory address, 
 wherein a first portion of the processor is to perform operations using only the compressed version of the full address and a second portion of the processor is to perform operations using the full address when the full address is required. 
 
     
     
       2. The processor as in  claim 1  further comprising:
 table synchronization logic to synchronize the first and second translation tables. 
 
     
     
       3. The processor as in  claim 1  wherein the pointer comprises an N-bit value and the portion of the full memory address comprises an M-bit value, where N<M. 
     
     
       4. The processor as in  claim 3  wherein N=3 and M=12. 
     
     
       5. The processor as in  claim 1  wherein using the translation tables to convert between the full address and a compressed version of the full address comprises:
 determining whether an entry exists for a portion of a full memory address; 
 if an entry exists, then using the pointer associated with that entry to create the compressed address; and 
 if an entry does not exist, then creating a new entry and using the pointer associated with that new entry to create the compressed address. 
 
     
     
       6. The processor as in  claim 5  wherein using the pointer to create the compressed address further comprises:
 removing the portion from the full memory address; and 
 replacing the portion with the pointer. 
 
     
     
       7. The processor as in  claim 1  further comprising:
 a system memory addressable by the full memory address. 
 
     
     
       8. The processor as in  claim 7  wherein the system memory is configured on a common die with the processor. 
     
     
       9. The processor as in  claim 1  wherein internal address structures are flushed when valid translation table entries are deallocated. 
     
     
       10. The processor as in  claim 1  comprising translation table tracking logic used to retain a subset of internal address structures when a translation table entry is deallocated. 
     
     
       11. A method comprising:
 populating one or more translation tables with a plurality of translation entries, each translation entry including a pointer value and storing a portion of a full memory address usable within a processor to address data and instructions, wherein the translation tables comprise a first translation table and a second translation table, the first and second translation tables being located at different processor pipeline stages, and wherein the first translation table is used for converting from full memory addresses to compressed memory addresses, and the second translation table is used for converting from compressed memory addresses to full memory addresses; and 
 using the translation tables to convert between the full address and a compressed version of the full address, the compressed version of the full address having the pointer value substituted for the portion of the full memory address, 
 performing operations in a first portion of the processor using only the compressed version of the full address and performing operations in a second portion of the processor using the full address when the full address is required. 
 
     
     
       12. The method as in  claim 11  further comprising:
 synchronizing the first and second translation tables. 
 
     
     
       13. The method as in  claim 11  wherein the pointer comprises an N-bit value and the portion of the full memory address comprises an M-bit value, where N <M. 
     
     
       14. The method as in  claim 13  wherein N=3 and M=12. 
     
     
       15. The method as in  claim 11  wherein using the translation tables to convert between the full address and a compressed version of the full address comprises:
 determining whether an entry exists for a portion of a full memory address; 
 if an entry exists, then using the pointer associated with that entry to create the compressed address; and 
 if an entry does not exist, then creating a new entry and using the pointer associated with that new entry to create the compressed address. 
 
     
     
       16. The method as in  claim 15  wherein using the pointer to create the compressed address further comprises:
 removing the portion from the full memory address; and 
 replacing the portion with the pointer.